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7165165 |
Anticipatory power control of memory
In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory...
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7155596 |
Electronic device and playback control method therefor
There is provided an electronic device including: a storage medium in which content data is divided into units of clusters and stored; a link information table that records the link structure of...
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7152153 |
Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction
A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single...
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7139867 |
Partially-ordered cams used in ternary hierarchical address searching/sorting
An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content addressable memories (CAMs) for...
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7133996 |
Memory device and internal control method therefor
A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second...
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7130984 |
First-in first-out memory system with shift register fill indication
An electronic device ( 10 ). The device comprises a memory structure ( 12 ) comprising an integer M of word storage locations. The device further comprises a write shift register (SR WT ) for...
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7111149 |
Method and apparatus for generating a device ID for stacked devices
A method for generating a unique device ID for each addressable device in a stack of multiple addressable devices by encoding a device ID for one device in the stack and determining a device ID for...
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7103750 |
Method and apparatus for finding repeated substrings in pattern recognition
A method and apparatus for compressing a reference pattern (RP) with repeated substrings by encoding produce compressed reference patterns (CRPs) with reduce storage requirements. Operation codes...
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7099345 |
Method and system for buffering a data packet for transmission to a network
Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory....
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7100019 |
Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values
A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface....
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7089401 |
Data relay controller
A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main...
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7082514 |
Method and memory controller for adaptive row management within a memory subsystem
A method and memory controller for adaptive row management within a memory subsystem provides metrics for evaluating row access behavior and dynamically adjusting the row management policy of the...
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7080236 |
Updating stack pointer based on instruction bit indicator without executing an update microinstruction
A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also...
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7073019 |
Method and apparatus for assembling non-aligned packet fragments over multiple cycles
A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data...
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7051183 |
Circuit for recording digital waveform data and method of doing the same
A circuit for recording digital waveform data includes (a) a first counter which counts the number of data constituting a first data sequence including a plurality of data different from one...
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7043623 |
Distributed memory computing environment and implementation thereof
A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other...
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7035995 |
Method and apparatus for performing a high speed binary search in time critical environments
A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary...
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7035960 |
Method for increasing memory in a processor
A method for increasing the internal memory in a processor. The method includes providing an extended memory in the processor, adding bits to data addresses and register addresses with an address...
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7032100 |
Simple algorithmic cryptography engine
A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design...
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7017028 |
Apparatus and method for updating pointers for indirect and parallel register access
An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e....
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7017027 |
Address counter control system with path switching
An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a...
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7000064 |
Data handling system
In one embodiment of the present invention, there is disclosed, a method of handling data which is being written to and stored in flash memory, wherein input data, comprising information data and...
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6976158 |
Repeat instruction with interrupt
A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of...
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6973551 |
Data storage system having atomic memory operation
A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method includes...
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6970526 |
Controlling the system time clock of an MPEG decoder
During decoding and processing of program clock reference (PCR) values in MPEG-2 transport streams, a first initial difference value is obtained by calculating a difference between a first detected...
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6970993 |
Architecture to relax memory performance requirements
The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be...
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6965980 |
Multi-sequence burst accessing for SDRAM
Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory...
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6952762 |
Data storage device with overlapped buffering scheme
A data storage device is disclosed that, in response to a data output request, outputs stored data beginning with a selected output start address. The disclosed data storage device is characterized...
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6950921 |
Method for operating an integrated memory unit partitioned by an external control signal
A method for operating an integrated memory unit having a memory cell field includes the steps of, before a memory access, partitioning the memory cell field into a plurality of memory areas, for...
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6941445 |
Resampling address generator
A resampling address generator updates period data in a resampling period address register when the periods of input and output clocks are not stable, and generates a read address by supplying the...
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6941421 |
Zero delay data cache effective address generation
A method and system for accessing a specified cache line using previously decoded base address offset bits, stored with a register file, which eliminate the need to perform a full address decode in...
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6931517 |
Pop-compare micro instruction for repeat string operations
A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired...
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6922771 |
Vector floating point unit
The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor...
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6918024 |
Address generating circuit and selection judging circuit
An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address...
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6912643 |
Method of flexibly mapping a number of storage elements into a virtual storage element
The present invention provides an architecture and method for increasing the performance and resource utilization of networked storage architectures by use of hardware-based storage element...
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6912616 |
Mapping addresses to memory banks based on at least one mathematical relationship
One embodiment of the invention is a memory controller that maps a received address to a memory location in a plurality of memory banks, the memory controller comprising: circuitry for calculating...
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6912646 |
Storing and selecting multiple data streams in distributed memory devices
Prior art storage techniques have certain limitations, including requiring additional external resources to implement and not making use of all of the available storage space. A method and...
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6892272 |
Method and apparatus for determining a longest prefix match in a content addressable memory device
A method and apparatus for determining a longest prefix match in a content addressable memory (CAM) device is described. The CAM device includes a CAM array that may be arbitrarily loaded with CIDR...
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6883088 |
Methods and apparatus for loading a very long instruction word memory
The ManArray processor is a scalable indirect VLIW array processor that defines two preferred architectures for indirect VLIW memories. One approach treats the VIM as one composite block of memory...
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6877082 |
Central processing unit including address generation system and instruction fetch apparatus
A disclosed address generation system includes a decrementer and a multiplexer. The decrementer produces a decremented address signal by subtracting a first integer value from an incremented...
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6871256 |
Method and arrangement in a stack having a memory segmented into data groups having a plurality of elements
In a data memory arrangement for a microprocessor system, in which the data memory is designed as a group memory composed of element memories in which data are storable in data groups having a...
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6857043 |
Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter
First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one...
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6851013 |
Fast program mode
A method of programming a memory. The method of one embodiment calls for sending a command to a memory device. The command requests the memory device to enter a program mode. A confirmation of the...
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6851039 |
Method and apparatus for generating an interleaved address
In the method of generating an interleaved address, each 2^i mod (p−1) value for i=0 to x−1 is stored. Here, p is a prime number dependent on a block size K of a data block being processed and...
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6839285 |
Page by page programmable flash memory
An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel....
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6834335 |
System and method for reducing transitions on address buses
An encoder and decoder provide coding of information communicated on buses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.
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6829694 |
Reconfigurable parallel look up table system
A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up...
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6820186 |
System and method for building packets
Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory....
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6820194 |
Method for reducing power when fetching instructions in a processor and related apparatus
In one disclosed embodiment an instruction loop having at least one instruction is identified. For example, each instruction can be a VLIW packet comprised of several individual instructions. The...
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6807619 |
Advancing bank pointer in prime numbers unit
The cache arrangement includes a cache that may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot...
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