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RE40904 Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer  
The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute...
7577799 Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture  
The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at...
7555629 Memory card providing hardware acceleration for read operations  
A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first...
7549037 Efficient off-host backup of a file set clone  
A method, system, computer system, and computer-readable medium that enable a secondary host that is not the file system host to create a backup of a clone file set that shares at least one data...
7549036 Management of access to data from memory  
Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command...
7543130 Digital signal processor for initializing a ram  
A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that...
7493450 Method of triggering read cache pre-fetch to increase host read throughput  
Exemplary systems and methods include pre-fetching data in response to a read cache hit. Various exemplary methods include priming a read cache with initial data, and triggering a read pre-fetch...
7490282 Method and apparatus of turbo encoder  
Briefly, an apparatus, a method and a wireless communication device are provided. The wireless communication device includes a turbo encoder to generate an encoded data block and a transmitter to...
7489583 Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays  
Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing...
7466623 Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof  
A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually...
7464250 Method to reduce disk access time during predictable loading sequences  
The invention discloses a method for loading data from a disk. The method may comprise comparing a current sequence of disk requests to data indicative of a previous disk request sequence....
7457894 Synchronization of non-sequential moving pointers  
A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed....
7454589 Data buffer circuit, interface circuit and control method therefor  
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
7421563 Hashing and serial decoding techniques  
A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and...
7409527 Bidirectional data storing method  
A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data...
7406569 Instruction cache way prediction for jump targets  
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
7395407 Mechanisms and methods for using data access patterns  
The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and...
7386675 Systems and methods for using excitement values to predict future access to resources  
Systems and methods using an excitement protocol enable prediction of which blocks of a resource to prefetch and store in memory. The system maintains a set of excitement values corresponding to...
7360040 Interleaver for iterative decoder  
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO)...
7343470 Techniques for sequentially transferring data from a memory device through a parallel interface  
Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address...
7340562 Cache for instruction set architecture  
A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is...
7290117 Memory having increased data-transfer speed and related systems and methods  
A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address...
7266671 Register addressing  
There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register...
7257651 Sequential data transfer detection using addresses of data transfer requests to control the efficiency of processing the data transfer requests  
A method of detecting sequential data transfer requests, includes determining whether a first data transfer request crosses a boundary address, and, if it does, determining if the first data...
7254692 Testing for operating life of a memory device with address cycling using a gray code sequence  
In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit...
7243209 Apparatus and method for speeding up access time of a large register file with wrap capability  
An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file...
7213126 Method and processor including logic for storing traces within a trace cache  
A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be...
7210020 Continuous interleave burst access  
A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either...
7206918 Address predicting apparatus and methods  
Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation...
7188231 Multimedia address generator  
Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with...
7174442 Data addressing  
A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential...
7174432 Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture  
The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at...
7171469 Apparatus and method for storing data in a proxy cache in a network  
In one embodiment, the invention provides an apparatus for caching data in a network, with the apparatus including a proxy cache configured to receive request for an object from a client and to...
7162563 Semiconductor integrated circuit having changeable bus width of external data signal  
A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address...
7159084 Memory controller  
A memory controller, such as a SDRAM controller, forms a queue of memory access requests to maximize efficient use of the bandwidth of the memory data bus. More specifically, the SDRAM controller...
7149862 Access control in a data processing apparatus  
A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage...
7146469 Method, apparatus, and system for improving memory access speed  
According to one embodiment of the invention, an apparatus comprises a high speed memory unit, a memory controller and an external bus interface (EBIF) unit coupled to the memory controller. The...
7143264 Apparatus and method for performing data access in accordance with memory access patterns  
An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access...
7139896 Linear and non-linear object management  
A linear and non-linear object management method and structure. A data structure on a computer-readable medium is used to store linear and non-linear objects in a range of memory of a volume. The...
7136988 Mass data storage library frame spanning for mixed media  
Disclosed are a system, a method, and an article of manufacture to provide for configuring an automated data storage library having one or more storage frames that operate with different types of...
7133997 Configurable cache  
A method, apparatus, and system for configuring an address bit in a cache formed on an integrated circuit. The method, apparatus, and system include the ability to configure the address bit as...
7117309 Method of detecting sequential workloads to increase host read throughput  
Exemplary systems and methods analyze cache data to detect a sequential workload to facilitate pre-fetching effectiveness. An exemplary address analysis module for sequential workload detection...
7103750 Method and apparatus for finding repeated substrings in pattern recognition  
A method and apparatus for compressing a reference pattern (RP) with repeated substrings by encoding produce compressed reference patterns (CRPs) with reduce storage requirements. Operation codes...
7093085 Device and method for minimizing puncturing-caused output delay  
Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to...
7080056 Automatic programming  
A method for generating a simple kind of computer based artificial consciousness, which means to give a in a computer running invention-pursuant program the capability to act and to know the...
7076578 Race free data transfer algorithm using hardware based polling  
A method and apparatus for a race free data transfer algorithm using hardware based polling. One disclosed method transfers information between a target device and a buffer which is one of a set of...
7058874 Interleaver address generator and method of generating an interleaver address  
An interleaver circuit architectures, which utilizes the relationship between intra-row elements in a matrix, in order to simplify the MOD computations necessary in an interleaver. The interleaver...
7051183 Circuit for recording digital waveform data and method of doing the same  
A circuit for recording digital waveform data includes (a) a first counter which counts the number of data constituting a first data sequence including a plurality of data different from one...
7028154 Procedure to reduce copy time for data backup from short-term to long-term memory  
Systems and methods for backup of data in redundant data storage systems. In this regard, one embodiment can be broadly summarized by a representative system that copies a block of data from a...
7023240 Data-driven clock gating for a sequential data-capture device  
A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit...
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