Matches 201 - 250 out of 258 < 1 2 3 4 5 6 >
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5737570 Memory unit including an address generator  
A memory unit includes a plurality of address ranges whose size and number are freely variable. For each address range, one address value is stored, as well as a start and an end address. The...
5699553 Memory accessing device for a pipeline information processing system  
A memory accessing device is connected to a central processing unit and a memory unit via a common bus. The memory accessing device accesses the memory unit independently of the central processing...
5689515 High speed serial data pin for automatic test equipment  
A tester that produces digital timing signals having fast data rates including multiple groups of timing generators, multiple "exclusive-or" gates, and an "or" gate. Each group of timing generators...
5689676 Sequential EEPROM writing apparatus which sequentially and repetitively replaces a head position pointer with a last position pointer  
A storage device incorporating an electrically erasable read only memory (EEPROM) or other data storage device having a limited number of total times of rewriting, has its useful like extended by...
5659698 Method and apparatus for generating a circular buffer address in integrated circuit that performs multiple communications tasks  
A circular buffer address generation unit (630) may be accomplished by first determining a potential next address (635) based on a current address (644) and an address offset value (646). Having...
5644704 Method and apparatus for verifying the contents of a storage device  
A method and apparatus for verifying the contents of a storage device. A number of steps are involved in performing the verification. First, non-sequential data is written into each unused memory...
5638528 Data processing system and a method for cycling longword addresses during a burst bus cycle  
A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), and second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*)....
5594913 High speed memory access system for a microcontroller with directly driven low order address bits  
A microcontroller which directly drives a memory with low order address bits during a fetch operation. Driving the low order address bits directly while the high order bits are latched during an...
5592639 Device and method for writing in a storage device of the queue type  
The invention principally relates to a device and to a method for writing in a storage device of the stack type. The invention relates to the use of stacks (1) of the first-in, first-out (FIFO)...
5590351 Superscalar execution unit for sequential instruction pointer updates and segment limit checks  
An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor...
5590307 Dual-port data cache memory  
A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high...
5586280 Method and apparatus for appending data to compressed records previously stored on a sequentially-accessible storage medium  
A method of appending data to compressed data stored on tape (10) in the form of records (CR n ) wherein compressed data is stored in groups (G n ) independently of the record structure of the data...
5584000 Addressing scheme for microcode store in a signal processor  
When the processing circuitry of a signal processor can handle data at a faster rate than the rate of arrival of signal units to be processed, the processor is able to execute a cycle of microcodes...
5559979 Table-based inter-system serialization control system  
An inter-system serialization control system comprising an external storage unit commonly connected to computer systems for storing, when a request for accessing a logical processing unit in the...
5537572 Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM)  
A cache memory controller and method for dumping the contents of a cache directory and a cache data random access memory (RAM) are described. In order to dump the contents of the cache directory,...
5535173 Data-storage device  
To resolve problems associated with the use of an AUDIO type memory with defective cells without concern for groups of defective cells in such memories, the sounds to be recorded are stored at...
5500930 System to decode instructions indicating the addresses of control codes and providing patterns to direct an electron beam exposure apparatus  
A decoder to decode input data which includes an instruction code. The decoder includes a high-order address generator which uses the instruction code in the generation of the high-order address,...
5487146 Plural memory access address generation employing guide table entries forming linked list  
A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer...
5471600 Address generating circuit using a base pointer of loop area  
An address generating circuit includes a latch circuit and two adder/subtractors. The inputs of the first adder/subtractor are from the latch circuit and from a distance relative to a value of a...
5463749 Simplified cyclical buffer  
An improved cyclical buffer having an integer M number of memory locations in respect of which a number STEP of consecutive memory locations are required to be accessed in a single operation and...
5463755 High-performance, multi-bank global memory card for multiprocessor systems  
A multi-bank global memory system (GMS) for use with a multiprocessor computer system having a global bus. The GMS includes up to four global memory cards (GMCs) connected to the global bus. The...
5461718 System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory  
A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system...
5448714 Sequential-access and random-access dual-port memory buffer  
For interfacing a random-access (microprocessor-type) device to a sequential-access type device, such as EISA (Extended Industry Standard Architecture)-bus-memory (RAM) cell array (110), employed...
5379410 Data generating apparatus generating consecutive data and having a data skip scheme and a method of operating the same  
A data generating apparatus for sequentially generating data includes a binary counter, a setting circuit, a match detecting circuit, and a selector group. The binary counter responds to a clock...
5349677 Apparatus for calculating delay when executing vector tailgating instructions and using delay to facilitate simultaneous reading of operands from and writing of results to same vector register  
Improved performance is obtained in computers of the type having vector registers which communicate with one or more functional units and common memory. As elements of a vector are read from a...
5276841 Audio/video data reproducing apparatus which generates end of data transfer signal and which transfers data after communication error without resetting address data  
An audio/video data reproducing apparatus reads out data from a first storage, which has its storage area equally divided into clusters and stores audio/video data on a cluster-by-cluster basis, to...
5274786 Microprocessor memory bus interface for inhibiting relatching of row address portions upon subsequent accesses including a same row address portion  
An interface unit which can reduce the hardware cost by interfacing a microprocessor with an inexpensive memory device with a smaller word size without compromising the overall performance. The...
5249277 Optimized performance memory method and system  
A system and method for optimizing the performance of a computer memory system substitutes faster memory for a certain portion of the main memory. The substituted memory section automatically...
5241662 Integrated circuit card member for use in data processing device  
A plug-in data cartridge for a printer or a similar device. The cartridge contains an addressable memory and an address generator. In response to a designation of a starting address, the address...
5212778 Message-driven processor in a concurrent computer  
A message-driven concurrent computer system stores incoming messages in a row buffer and then in a queue in main memory. A translator cache is also located in main memory, and output from the cache...
5206940 Address control and generating system for digital signal-processor  
A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing...
4954951 System and method for increasing memory performance  
The improved memory system can use various memories, such as CCDs and RAMs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is...
4918587 Prefetch circuit for a computer memory subject to consecutive addressing  
A computer memory prefetch architecture for accelerating the rate at which data can be accessed from memory and transmitted to a processor when successive addresses are numerically consecutive....
4835736 Data acquisition system for capturing and storing clustered test data occurring before and after an event of interest  
A memory pointer circuit includes a plurality of counters and a programmable logic array for controlling the counters to generate addresses for an acquisition memory. The programmable logic array...
4835733 Programmable access memory  
An integrated circuit memory includes processing capability on the same chip, on one or both of an address path and data path between a set of access registers and a memory array so that an address...
4812974 Data processing apparatus for processing list vector instructions  
List operation on a vector in which the number of an element of a vector operand is represented by an element of another vector operand is to be performed with a general-purpose computer system...
4764895 Data processor for changing the sequential format of inputted records  
A format-changing data processing system is capable of storing successive input records (data words) in a random access memory and of retrieving the data words from the memory in accordance with...
4706188 Method and apparatus for reading samples of a time-dependent signal in a data processing system  
A method and apparatus for preparing samples of a time-dependent signal (Se) in a data processing system which comprises an arithmetic unity (1), a control unit (2), a memory (3) and an address...
4620277 Multimaster CPU system with early memory addressing  
A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory...
4556960 Address sequencer for overwrite avoidance  
An address sequencer utilizes binary words generated by Exclusive-OR addition of Gray code words to linear code words to produce a sequence of computer or memory addresses such that the addresses...
4550431 Address sequencer for pattern processing system  
An address sequencer produces an address stream which includes a plurality of interleaved sequences of addresses. Each sequence is a function of input data which is received when an input pattern...
4458332 Method of executing an address-jump command in a stored-program sequential-control system for processing machines, and in particular for industrial sewing machines, and sequential-control circuitry for the practice of the method  
In a method and circuit for executing an address jump command in a stored-program sequential-control system for operating machine tools or the like, an address counter is settable to a desired...
4438493 Multiwork memory data storage and addressing technique and apparatus  
A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by...
4396981 Control store apparatus having dual mode operation handling mechanism  
A writeable control store in a data processing system is provided with a dual mode capability. Coupled with the control store in the system is a central processing unit which may provide the next...
4380053 Memory addressing system for sequentially accessing all memory addresses in a memory area  
An improved memory addressing system is incorporated in an electronic calculator having input keys for entering numerical data, operational instructions and memory control instructions, a memory...
4370733 Pattern generation system  
A display system employs electronic components for deriving and supplying display control signals, preferably in the form of multi-bit display control words, to control a display device. The...
4370729 Microprogram sequencer  
A microprogram sequencer for generating in a proper sequence the addresses of the successive microinstructions used in executing a given machine instruction includes a PROM next address generator...
4366539 Memory controller with burst mode capability  
A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of...
4361869 Multimode memory system using a multiword common bus for double word and single word transfer  
A memory subsystem couples to a double wide word bus in common with a number of central processing units for processing memory requests received therefrom. The subsystem includes at least a pair of...
4352165 Apparatus for storing and retrieving data  
An automated artwork generation system employs a video display and a microprocessor for verifying and editing data derived from a digitizer and utilized by a photoplotter. The system includes a...
Matches 201 - 250 out of 258 < 1 2 3 4 5 6 >