Matches 151 - 200 out of 258 < 1 2 3 4 5 6 >
Match Document Document Title
6141742 Method for reducing number of bits used in storage of instruction address pointer values  
Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction...
6141741 Computer system with a shared address bus and pipelined write operations  
A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory...
6138227 Device for the jump-like addressing of specific lines of a serially operating digital memory  
A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding...
6122718 Column address counter with minus two subtractor for address compare  
The present invention is a method and circuit for providing a burst address counter with a fast burst-done signal. In a preferred embodiment, a synchronous memory device includes a counter for...
6108746 Semiconductor memory having an arithmetic function and a terminal arrangement for coordinating operation with a higher processor  
A display apparatus performs pixel density conversion processing, such as enlargement, reduction, and rotation, on an original image and displays a resultant image an image processing apparatus...
6094732 Shared memory controller having an address error detector  
A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write...
6088781 Stride instruction for fetching data separated by a stride amount  
A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a...
6084831 Apparatus and method of averaging disk transfer rate including division of disks into disks accessible in a radially inward direction and disks accessible in a radially outward direction  
A disc control apparatus handles an even number of disc-shaped recording mediums run in rotation at a constant angular velocity and to which addresses are accorded for incrementing from an inner...
6081853 Method for transferring burst data in a microprocessor  
A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache...
6078996 Method for increasing the speed of data processing in a computer system  
Method for increasing data-processing speed in computer systems containing at least one microprocessor, a memory device, and a so-called cache connected to the processor, in which the cache is...
6076138 Method of pre-programming a flash memory cell  
(The present invention discloses) a method of pre-programming a flash memory cell. According to the present invention, it makes it possible to execute a continuous programming by performing a...
6070166 Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit  
A method for compressing a plurality of contiguous addresses for storage in a queue. The method includes recognizing that a first address of the plurality of addresses is an individual address that...
6058464 Circuits, systems and method for address mapping  
An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface...
6055622 Global stride prefetching apparatus and method for a high-performance processor  
A method and hardware apparatus for data prefetching. In one embodiment, the method of the present invention comprises first calculating a local stride value by computing the value between two...
6052768 Circuit and method for modulo address generation with reduced circuit area  
The present invention relates to a modulo address generator and method thereof. The apparatus includes an adder which adds a current address value and an address increment value to generate an...
6049858 Modulo address generator with precomputed comparison and correction terms  
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit...
6047364 True modulo addressing generator  
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector...
6047366 Single-instruction multiple-data processor with input and output registers having a sequential location skip function  
A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store...
6038650 Method for the automatic address generation of modules within clusters comprised of a plurality of these modules  
A method of automatic address generation by units within clusters of a plurality of such units in which individual configurable elements of a unit can be addressed. It is thus possible to address...
6035384 Solid state disk drive address generator with multiplier circuit  
An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number,...
6014731 Disk control method and control apparatus capable of lowering data transfer load of computer by accessing a continuous, larger head portion of data, allocating addresses within empty time, and responding to priority orders of data  
In a storage disk control apparatus, a load of a computer caused by transferring data is reduced, and a waiting time until a data transfer operation is commenced is shortened. In the disk control...
5983311 Sequential memory accessing circuit and method of addressing two memory units using common pointer circuit  
A sequential memory access circuit for access to various memory units is provided. The sequential memory access circuit is coupled between an external system and at least two memory units including...
5958040 Adaptive stream buffers  
The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting...
5950233 Interleaved burst address counter with reduced delay between rising clock edge and burst address transfer to memory  
A burst address sequencer and method for providing sequential addresses to a memory which operates in response to a clock signal. The burst address sequencer includes a plurality of two-stage...
5943693 Algorithmic array mapping to decrease defect sensitivity of memory devices  
A method and apparatus for addressing a memory device are described. A first logical address is translated into a first physical address to access a first storage location at a first row and a...
5940875 Address pattern generator for burst address access of an SDRAM  
An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential...
5940874 Memory device speed tester  
A memory speed testing circuit including a memory addressing circuit (11, 13, 15) for sequentially providing to the address input of the memory device a binary address A and a binary address A...
5933861 Parallel memory device for image processing utilizing linear transformation  
A parallel memory device for an image processing utilizing a linear transformation, capable of achieving simultaneous access in either of various access forms which uses simple hardware and is...
5918253 Memory address generator  
An address generator has a designating value storing section for storing a designating value for designating each of register sections of an offset register into an address register. The address...
5911153 Memory design which facilitates incremental fetch and store requests off applied base address requests  
A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built...
5909704 High speed address generator  
An address generator (10) adapted for use with a first address source (12) and a second address source (14). The inventive generator (10) includes a first circuit (18-36) for selectively applying...
5906003 Memory device with an externally selectable-width I/O port and systems and methods using the same  
A memory device for storing variable width data words. The memory device (200) comprises an array (201) of memory cells, an address latch (207) for receiving and latching a first address word from...
5897667 Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner  
A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to...
5895502 Data writing and reading method for a frame memory having a plurality of memory portions each having a plurality of banks  
A data writing and reading method for a frame memory which provides a high speed data access by using a memory which is divided into a plurality of portions each of which has a plurality of banks....
5894549 System and method for fault detection in microcontroller program memory  
A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new...
5845083 MPEG encoding and decoding system for multimedia applications  
A multimedia data encoding and decoding system capable of handling various types of data arranged in variable-size blocks. Frames of image, graphics and text data are supplied to a frame buffer. In...
5835970 Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses  
An improved burst address generator that is coupled to a memory array receives as its inputs a N-bit start address and dynamically generates a burst sequence of 2 N decoded addresses. The burst...
5835971 Method and apparatus for generating addresses in parallel processing systems  
An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of...
5835972 Method and apparatus for optimization of data writes  
An improved method for performing memory writes from a processor in a personal computer system is provided whereby single writes are combined into burst writes based on detection of suitable write...
5828820 Mirror disk control method and mirror disk device  
There is provided by the present invention a mirror disk device, in which specific numbers identical to those written in disks and name of a drive used as for a master disk are recorded in a set-up...
5828877 Circuit and method for optimizing creation of a compressed main memory image  
A computer system having a central processing unit ("CPU"), a main memory divisible into allocable units, a secondary storage unit and an operating system for allocating the allocable units to...
5802389 Expansion module address method and apparatus for a programmable logic controller  
An expansion module address method and apparatus for a Programmable Logic Controller (PLC) is taught. Briefly stated, a PLC base unit sends an address to an expansion module or modules attached...
5802566 Method and system for predicting addresses and prefetching data into a cache memory  
A Method for increasing data-processing speed in computer systems containing at least one microprocessor (1), a memory device (3), and a cache (2,4) connected to the processor, in which the cache...
5787496 Digital signal processor having a partitioned memory with first and second address areas for receiving and storing data in sychronism with first and second sampling clocks  
A digital signal processor includes first and second counters which increment from each initial address value in first and second address areas synchronous with first and second sampling clock...
5778415 Apparatus, systems and methods for controlling electronic memories  
Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of...
5771369 Memory row redrive  
Improved memory access is provided for use when addressing dynamic random access modules (DRAMs). Both the memory contoller and the main memory hardware remember the row address of the last access....
5765212 Memory control circuit that selectively performs address translation based on the value of a road start address  
A memory control circuit improves the read speed of a program memory stored in a ROM. The memory control circuit includes a memory divided into four blocks, an address translation circuit for...
5765219 Apparatus and method for incrementally accessing a system memory  
Data storage apparatus comprises: a memory having a plurality of addressable memory locations for storage of data items and memory address input means for receiving addresses of locations to be...
5761690 Address generation apparatus and method using a peripheral address generation unit and fast interrupts  
Data block identification within a processor 100 may be accomplished when the processor 100 receives an interrupt while performing a main set of operational codes. Upon receiving the interrupt, the...
5754819 Low-latency memory indexing method and structure  
A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by...
Matches 151 - 200 out of 258 < 1 2 3 4 5 6 >