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7610432 |
Method and apparatus for assigning alias node names and port names within a tape library
A tape library apparatus comprising a plurality of FC drives. A host computer and a fiber channel switch portion are connected with an optical fiber cable through respective fiber channel...
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7606994 |
Cache memory system including a partially hashed index
In one embodiment, a cache memory system includes a cache memory coupled to a cache controller. The cache memory controller may receive an address and generate an index value corresponding to the...
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7587576 |
Parameter storing method, parameter storage device, multi-body problem processing apparatus, and address generator circuit
The object of the present invention is the reduction of memory capacity in a multi-body problem processing apparatus. In a parameter storing method in multi-body problem processing for performing a...
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RE40904 |
Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer
The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute...
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7571299 |
Methods and arrangements for inserting values in hash tables
Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in...
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7558941 |
Automatic detection of micro-tile enabled memory
In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory...
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7555629 |
Memory card providing hardware acceleration for read operations
A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first...
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7549036 |
Management of access to data from memory
Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command...
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7546430 |
Method of address space layout randomization for windows operating systems
A system and method for address space layout randomization (“ASLR”) for a Windows operating system is disclosed. The address space layout includes one or more memory regions that are identified...
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7539844 |
Prefetching indirect array accesses
A method for prefetching data from an array, A, the method including: detecting a stride, dB, of a stream of index addresses of an indirect array, B, contents of each index address having...
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7523294 |
Maintaining original per-block number of instructions by inserting NOPs among compressed instructions in compressed block of length compressed by predetermined ratio
The present invention discloses a method for compressing instruction codes. This method comprises: compressing an instruction block including a plurality of instructions according to...
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7516298 |
Sparse table compaction method
A method and system of sparse table compaction is disclosed. A repeating data pattern may be detected in a large data structure, identifying the large data structure as a sparse table. The large...
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7506105 |
Prefetching using hashed program counter
Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used...
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7502909 |
Memory address generation with non-harmonic indexing
A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register,...
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7493450 |
Method of triggering read cache pre-fetch to increase host read throughput
Exemplary systems and methods include pre-fetching data in response to a read cache hit. Various exemplary methods include priming a read cache with initial data, and triggering a read pre-fetch...
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7480783 |
Systems for loading unaligned words and methods of operating the same
Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a...
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7466623 |
Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof
A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually...
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7464250 |
Method to reduce disk access time during predictable loading sequences
The invention discloses a method for loading data from a disk. The method may comprise comparing a current sequence of disk requests to data indicative of a previous disk request sequence....
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7457936 |
Memory access instruction vectorization
A compilation method includes converting memory access instructions that read or write less than a minimum data access unit (MDAU) to memory access instructions that read or write a multiple of the...
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7454589 |
Data buffer circuit, interface circuit and control method therefor
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
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7447862 |
Memory system and timing control method of the same
A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal...
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7437531 |
Testing memories
Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for...
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7434216 |
Update package generator that employs genetic evolution to determine bank order
Disclosed herein is an update package generator which may employ a bank order determination module to determine an optimum bank order of memory banks of a binary image of at least one of firmware...
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7421563 |
Hashing and serial decoding techniques
A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and...
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7421540 |
Method, apparatus, and program to efficiently calculate cache prefetching patterns for loops
A mechanism is provided that identifies instructions that access storage and may be candidates for cache prefetching. The mechanism augments these instructions so that any given instance of the...
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7418573 |
Address generation apparatus and operation apparatus
An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An...
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7415584 |
Interleaving input sequences to memory
An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while...
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7409527 |
Bidirectional data storing method
A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data...
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7409472 |
Device controller and input/output system
An input/output request sent from a host is once cued through a channel adapter and is then transferred to a resource manager and is cued, and the cuing is distributed. Even if sequential...
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7406569 |
Instruction cache way prediction for jump targets
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
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7404055 |
Memory transfer with early access to critical portion
In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred...
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7400591 |
Method of creating an address and a discontiguous mask for a network security policy area
A method of creating a discontiguous address plan for an enterprise is provided which includes determining a hierarchy of routing optimization for an enterprise, determining a number of route...
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7395407 |
Mechanisms and methods for using data access patterns
The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and...
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7395406 |
System and method of large page handling in a virtual memory system
A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a...
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7394494 |
Sub-sampling apparatus and method and image sensor employing the same
The present disclosure relates to an address sub-sampling apparatus and method, and an image sensor employing the same. An address sub-sampling apparatus includes a counting unit that generates a...
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7386675 |
Systems and methods for using excitement values to predict future access to resources
Systems and methods using an excitement protocol enable prediction of which blocks of a resource to prefetch and store in memory. The system maintains a set of excitement values corresponding to...
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7383416 |
Method for setting a second rank address from a first rank address in a memory module
A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first...
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7380099 |
Apparatus and method for an address generation circuit
A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a...
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7380084 |
Dynamic detection of block boundaries on memory reads
In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for...
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7373480 |
Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table
A method and apparatus for determining a stack distance histogram for running software. The method may include receiving a plurality of memory references each including a corresponding address. The...
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7340584 |
Sequential nibble burst ordering for data
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode...
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7340583 |
Method and apparatus of controlling memory device
An address decoder 10 decodes an address signal 20 to generate access signals 22, 24 . An OR circuit implements a logical OR of the signals 22, 24 to generate a chip enable signal. An...
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7313668 |
Immediate virtual memory
Various embodiments of the present invention provide for immediate allocation of virtual memory on behalf of processes running within a computer system. One or more bit flags within each...
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7293139 |
Disk array system generating a data guarantee code on data transferring
To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a...
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7290117 |
Memory having increased data-transfer speed and related systems and methods
A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address...
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7266671 |
Register addressing
There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register...
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7260096 |
Method and router for forwarding internet data packets
The Internet data defining destinations accessible by a router are partitioned into a portion containing the address search information and a portion containing forwarding option data. The address...
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7246204 |
Pre-fetch control device, data processing apparatus and pre-fetch control method
The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory...
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7243209 |
Apparatus and method for speeding up access time of a large register file with wrap capability
An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file...
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7222040 |
Methods and apparatus for producing an IC identification number
Methods and apparatus provide for: testing a static random access memory (SRAM) to obtain performance data on the SRAM; and using the performance data as at least a basis of a identification number.
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