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7617400 |
Storage partitioning
In one embodiment, a method is provided that may include one or more operations. One of these operations may include partitioning, in response at least in part to a request from a remote authority,...
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7617382 |
Method and apparatus for decompressing relative addresses
A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed...
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7506128 |
Smart card with volatile memory file subsystem
An integrated circuit (IC) module allows volatile data generated by applications to be stored within volatile data files in the volatile memory. A file system tracks the location of all data files...
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7461205 |
Performing useful computations while waiting for a line in a system with a software implemented cache
Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes...
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7406569 |
Instruction cache way prediction for jump targets
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
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7343471 |
Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions
Instructions of a program are stored in compressed form in a program memory ( 12 ). In a processor which executes the instructions, a program counter ( 50 ) identifies a position in the program...
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7146457 |
Content addressable memory selectively addressable in a physical address mode and a virtual address mode
Systems and methods are provided for searching at least one content addressable memory entry associated with a content addressable memory (CAM). A given content addressable memory entry comprises a...
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7143265 |
Computer program product memory access system
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred...
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7103749 |
System and method for managing memory
A new memory tuple is described that creates both a handle as well as a reference to an item within the handle. The reference is created using an offset value that defines the physical offset of...
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7069415 |
System and method to automatically stack and unstack Java local variables
A processor preferably comprises a processing core that generates memory addresses to access a memory and on which a plurality of methods operate, a cache coupled to the processing core, and a...
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7051138 |
Interrupt-processing system for shortening interrupt latency in microprocessor
The invention relates to a data processing system which comprises a memory module and a microprocessor. The memory modules comprise at least one low-speed memory and one high-speed memory; both...
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7039789 |
Circular addressing algorithms providing increased compatibility with one or more higher-level programming languages
Logic for circular addressing providing increased compatibility with higher-level programming languages accesses a base pointer pointing to a first element of an array including a number of...
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7010665 |
Method and apparatus for decompressing relative addresses
A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed...
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6986014 |
System and method for using a vendor-long descriptor in ACPI for the chipset registers
A system and method for using memory mapped I/O (MMIO) to manage system devices is provided. A parent device in the ACPI namespace uses (MMIO) to identify the memory addresses of its children...
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6957322 |
Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion
A microcode instruction unit for a processor may include a microcode memory having entries for storing microcode instructions. A decoder for the microcode memory may decode microcode addresses to...
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6934828 |
Decoupling floating point linear address
A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of...
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6851037 |
Method of utilization of a data storage array, and array controller therefor
A number of virtual areas with virtual addresses of storage locations within the virtual areas are allocated to a data storage array, having a total physical storage capacity. Physical addresses...
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6816959 |
Memory access system
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred...
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6816889 |
Assignment of dual port memory banks for a CPU and a host channel adapter in an InfiniBand computing node
An InfiniBand™ computing node includes a dual port memory configured for storing data for a CPU and a host channel adapter in a manner that eliminates contention for access to the dual port...
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6775756 |
Method and apparatus for out of order memory processing within an in order processor
A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline...
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6732258 |
IP relative addressing
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an...
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6658553 |
Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space
A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional...
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6654868 |
Information storage and retrieval system
Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in...
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6618803 |
System and method for finding and validating the most recent advance load for a given checkload
The present invention discloses a system and method for simultaneously identifying a most recent advanced load instruction employing a particular register and determining whether the instruction...
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6584557 |
Processor and method for generating a pointer
A processor is provided for calculating an output pointer to a first data item by combination of an input pointer to a second data item with an offset. The processor includes logic for generating,...
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6567908 |
Method of and apparatus for processing information, and providing medium
An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU...
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6519692 |
Method for updating a pointer to access a memory address in a DSP
A processor coupled to a memory for providing a pointer in order to access a corresponding memory address, the pointer being updated by adding a predetermined increment according to logic integral...
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6470439 |
FIFO memory control circuit
The present invention relates to a FIFO (First In First Out) memory control circuit for controlling FIFO memory which is used in various electronic devices. Specifically, the present invention...
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6438680 |
Microprocessor
When a decision circuit ( 217 ) incorporated in a control circuit ( 21 ) in an instruction decode unit ( 2 ) in a microprocessor ( 1 ) decides that an integer operation unit ( 4 ) can not execute a...
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6345336 |
Instruction cache memory includes a clock gate circuit for selectively supplying a clock signal to tag RAM to reduce power consumption
An instruction cache memory ( 12 ) includes a clock gate circuit ( 26 ) for controlling the supply of a clock signal (CLK) to tag RAM ( 22 ). The clock gate circuit ( 22 ) supplies the clock signal...
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6311258 |
Data buffer apparatus and method for storing graphical data using data encoders and decoders
A data buffer apparatus stores first data objects containing a plurality of first data items and second data objects containing one or more second data items in a number of different ways depending...
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6272615 |
Data processing device with an indexed immediate addressing mode
A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry...
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6189086 |
Data processing apparatus
A microprocessor apparatus executes a program including an instruction which indicates an address for taking out an operand from a main memory in a predetermined addressing mode which belongs to a...
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6173385 |
Address generator for solid state disk drive
An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number,...
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6141740 |
Apparatus and method for microcode patching for generating a next address
A superscalar microprocessor implements a microcode instruction unit that patches existing microcode instructions with substitute microcode instructions. A flag bit is associated with each line of...
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6088781 |
Stride instruction for fetching data separated by a stride amount
A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a...
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6081869 |
Bit-field peripheral
A bit field system is disclosed which includes a processor as well as a bit field peripheral device which is accessed via dedicated bit field addresses. Such a system efficiently executes bit field...
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5966722 |
Method and apparatus for controlling multiple dice with a single die
A method and apparatus for controlling an integrated circuit (IC) die with another IC die. The present invention uses a processor to control the operation of a cache memory die. In this manner, the...
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5960467 |
Apparatus for efficiently providing memory operands for instructions
An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the...
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5903908 |
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache...
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5881260 |
Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction
An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction...
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5835971 |
Method and apparatus for generating addresses in parallel processing systems
An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of...
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5835968 |
Apparatus for providing memory and register operands concurrently to functional units
An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the...
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5813045 |
Conditional early data address generation mechanism for a microprocessor
An apparatus is provided, including one or more early address generation units which attempt to perform data address generation upon decode of an instruction which includes a memory operand. The...
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5809271 |
Method and apparatus for changing flow of control in a processor
A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow...
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5729723 |
Data processing unit
A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program. To this end, the data processing...
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5678020 |
Memory subsystem wherein a single processor chip controls multiple cache memory chips
A memory subsystem and method for controlling an integrated circuit (IC) die with another IC die, and a computer system for use with the memory subsystem. The computer system uses a processor die...
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5666508 |
Four state two bit recoded alignment fault state circuit for microprocessor address misalignment fault generation
An apparatus for controlling address alignment fault generation employing a recoded two bit structure. This alignment fault state circuit stores one of four states corresponding to whether the...
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5649144 |
Apparatus, systems and methods for improving data cache hit rates
A processing system is provided which generates a memory address and presents the memory address to a cache to retrieve corresponding data when such corresponding data is encached therein. The...
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5617558 |
Method of executing a series of computer code operations that must be completed without interruption by a page fault during execution
The time lost in unnecessarily checking for the presence of all memory references required by a special section of code in an operating system before the program is run and which dynamically...
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