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RE41012 |
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
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7577818 |
Microprocessor program addressing arrangement having multiple independent complete address generators
An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an...
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7571076 |
Performance monitor device, data collecting method and program for the same
A performance monitor device includes an input unit to input both of address information and event occurrence information, an address mask unit to determine an address area to which each piece of...
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7549036 |
Management of access to data from memory
Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command...
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7533242 |
Prefetch hardware efficiency via prefetch hint instructions
A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint information to a processor enabled to...
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7523261 |
Method and circuit arrangement for adapting a program to suit a buffer store
A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a...
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7502909 |
Memory address generation with non-harmonic indexing
A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register,...
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7502725 |
Method, system and computer program product for register management in a simulation environment
A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed...
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7464188 |
Computer system controlling accesses to storage apparatus
Since no control of accesses made by a computer as accesses to a storage apparatus is executed, the computer can be used illegally to steal and improperly change data stored in the storage...
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7447871 |
Data access program instruction encoding
A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit...
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7406569 |
Instruction cache way prediction for jump targets
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
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7401202 |
Memory addressing
Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to...
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7398370 |
Information processing apparatus and method
In an information processing apparatus, a program processing unit executes a program described as an object-oriented language executed by a platform-independent machine language. A monitor unit...
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7386702 |
Systems and methods for accessing thread private data
Systems and methods are provided for accessing thread private data in a computer. In one embodiment, a method is provided for accessing thread private data in a computer for a program executed by...
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7366882 |
Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions
A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.
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7360058 |
System and method for generating effective address
Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes...
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7356811 |
Method and apparatus for referencing a constant pool in a java virtual machine
A method, apparatus, and computer instructions for referencing a constant pool. A determination is made as to whether a bytecode references the constant pool. A relative offset to the constant pool...
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7308556 |
Device and method for writing data in a processor to memory at unaligned location
A device for writing data in a processor to memory at unaligned location. The data is stored in an internal register of the processor for writing to unaligned addresses of a memory partitioned by...
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7308555 |
Processor-based structure and method for loading unaligned data
A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third...
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7308553 |
Processor device capable of cross-boundary alignment of plural register data and the method thereof
A processor device capable of cross-boundary alignment of plural register data and the method thereof. The processor includes a decoder to decode a multiple shift instruction, a register unit with...
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7308554 |
Processor-based automatic alignment device and method for data movement
A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third...
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7302524 |
Adaptive thread ID cache mechanism for autonomic performance tuning
An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits...
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7234025 |
Microprocessor with repeat prefetch instruction
A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction....
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7152147 |
Storage control system and storage control method
A computer system comprises a primary volume 22 P having a plurality of storage blocks P, and a differential volume 22 D having a plurality of storage blocks D. Differential data corresponding to...
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7136987 |
Memory configuration apparatus, systems, and methods
An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such...
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7133996 |
Memory device and internal control method therefor
A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second...
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7093085 |
Device and method for minimizing puncturing-caused output delay
Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to...
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7080056 |
Automatic programming
A method for generating a simple kind of computer based artificial consciousness, which means to give a in a computer running invention-pursuant program the capability to act and to know the...
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7069393 |
Storage system providing file aware caching and file aware remote copy
A computer system in which a host computer is connected to a storage unit, the storage unit operating in a unit of a file. A file attribute control unit and the storage unit execute the processing...
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7032100 |
Simple algorithmic cryptography engine
A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design...
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6978357 |
Method and apparatus for performing cache segment flush and cache segment invalidation operations
A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a...
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6965987 |
System and method for handling load and/or store operations in a superscalar microprocessor
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
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6950922 |
Data extraction/insertion method and device in digital signal processor
A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a...
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6941444 |
Branch prediction method and apparatus
A computer has its programs in instructions and operand descriptors to specify the operands of the instructions. Apparatus for identifying data coherency and encaching requirements and providing...
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6934828 |
Decoupling floating point linear address
A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of...
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6931517 |
Pop-compare micro instruction for repeat string operations
A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired...
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6931508 |
Device and method for information processing
In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder...
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6877069 |
History-based carry predictor for data cache address generation
An address translation logic and method for generating an instruction's operand address. The address generation logic includes an address generation circuit having adders that perform partial sum...
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6862676 |
Superscalar processor having content addressable memory structures for determining dependencies
A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an...
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6851033 |
Memory access prediction in a data processing apparatus
The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an...
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6816889 |
Assignment of dual port memory banks for a CPU and a host channel adapter in an InfiniBand computing node
An InfiniBand™ computing node includes a dual port memory configured for storing data for a CPU and a host channel adapter in a manner that eliminates contention for access to the dual port...
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6799227 |
Dynamic configuration of a time division multiplexing port and associated direct memory access controller
An apparatus comprising a transmit data path, a receive data path, a first circuit and a second circuit. The first circuit may be configured to transfer data between a first interface and the...
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6779100 |
Method and device for address translation for compressed instructions
A computer system for storing corresponding instruction blocks in a compressed form in a main memory and in an uncompressed form in an instruction cache. The instruction cache line addresses for...
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6775756 |
Method and apparatus for out of order memory processing within an in order processor
A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline...
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6775764 |
Search function for data lookup
A SEARCH function preferably built into the instruction set of a microprocessor for quickly and efficiently searching a plurality of memory locations. Data from a significant number of memory...
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6760814 |
Methods and apparatus for loading CRC values into a CRC cache in a storage controller
Methods and structure for loading a CRC value cache memory in a storage controller on the fly to reduce overhead processing associated with access to system memory to load the CRC value cache...
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6754807 |
System and method for managing vertical dependencies in a digital signal processor
An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of...
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6745314 |
Circular buffer control circuit and method of operation thereof
A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes:...
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6745320 |
Data processing apparatus
There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a...
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6732258 |
IP relative addressing
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an...
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