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7617379 Multi-hit control method for shared TLB in a multiprocessor system  
The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an...
7613669 Method and apparatus for storing pattern matching data and pattern matching method using the same  
A method and apparatus for storing pattern matching data and a pattern matching method using the method and apparatus are provided. The method of storing original data for pattern matching in a...
7594145 Improving performance of a processor having a defective cache  
In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The...
7552305 Dynamic and real-time management of memory  
Dynamically allocated memory is managed in real-time. This real-time management capability enables an invalid access of the dynamically allocated memory to be detected at the time the invalid...
7536521 Computer storage device providing implicit detection of block liveness  
A disk drive or similar storage medium uses a semantic understanding of its associated file system to monitor file metadata and derive block liveness normally only known by the file system....
7526628 Optimizing cache efficiency within application software  
The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and...
7523291 System and method for testing for memory address aliasing errors  
Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by...
7523288 Dynamic fragment mapping  
A dataset is divided into pieces and stored at multiple locations and the system dynamically increases or decreases the number of storage locations where the pieces of the data set may be stored. A...
7519792 Memory region access management  
A memory region access management technique. More particularly, at least one embodiment of the invention relates to a technique to partition memory between two or more operating systems or other...
7512756 Performance improvement for block span replication  
The portion of a source block storage resource to be replicated, and the corresponding portion of the block storage resource being written to, are each divided into a predefined number of...
7467265 System and method for block conflict resolution within consistency interval marker based replication  
One goal of consistency interval replication is to achieve a consistent copy of data generated by independent streams of writes from nodes in a clustered/distributed environment. Two writes to the...
7447845 Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality  
A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array,...
7426625 Data processing system and computer program product for support of system memory addresses with holes  
A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating...
7424576 Parallel cachelets  
Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and...
7409525 Implicit locks in a shared virtual memory system  
A technique coordinates access to shared data on a remote device from a local device having local physical memory. The technique involves observing a page table entry (PTE) on the remote device....
7398361 Combined buffer for snoop, store merging, load miss, and writeback operations  
In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests...
7395380 Selective snooping by snoop masters to locate updated data  
A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less...
7395405 Method and apparatus for supporting address translation in a virtual machine environment  
In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which...
7386643 Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions  
A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict...
7349348 Method and apparatus for determining a network topology in the presence of network address translation  
The present invention may be used for determining a topology of a network in the presence of network address translation. From an active client behind a translating device, communications are...
7330961 Cache control method and processor system  
A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache...
7266652 System and method for managing data consistency between different data volumes on one or more data storage systems in a data storage environment  
This invention enables managing data consistency between different data volumes by managing I/O traffic in a data storage environment. A methodology for managing data consistency, in accordance...
7251719 Recording medium playback apparatus  
In one aspect of the invention, text data recorded on a CD conforming to the CD-TEXT format is displayed using a minimum amount of memory. Storage capacity to be used per data item is calculated by...
7240183 System and method for detecting instruction dependencies in multiple phases  
Systems and methods for determining dependencies between processor instructions in multiple phases. In one embodiment, a partial comparison is made between the addresses of a sequence of...
7222221 Maintaining coherency of derived data in a computer system  
A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer...
7177980 Cache storage system and method  
A cache storage system and method are provided for saving storage space in a cache, the system and method for use in a data storage system having multiple storage devices and multiple virtual...
7143079 Integrated composite data base system  
Companies and other organizations store extensive datasets having overlapping data contents in different data base systems whose data base structures are incompatible with one another. The...
7133995 Dynamic page conflict prediction for DRAM  
A memory controller may be implemented using dynamic page conflict prediction to control the closure of memory pages. A memory controller may include a page history register configured to store a...
7130983 System and method for reference count regeneration  
In a disk-based data storage system, a controller configured to control a reference count regeneration operation, the controller includes a control register, an address register, a status register,...
7124276 Optimizing cache efficiency within application software  
The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and...
7117330 Synchronization techniques in a multithreaded environment  
Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer...
7096341 System and method for reference count regeneration  
In a data storage system in which there can be multiple references to a single instance of an object, a method for regenerating the number of references to each object instance. The method includes...
7089376 Reducing snoop response time for snoopers without copies of requested data via snoop filtering  
In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering...
7076628 Microprocessor memory space allocation management  
A method for identification of memory assignment conflicts in the assignment of memory location addresses to a set of buffers. Programs run in embedded processors using buffers in a fixed storage...
7073047 Control chip and method for accelerating memory access  
A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of...
7020761 Blocking processing restrictions based on page indices  
Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an...
6993638 Memory access device and method using address translation history table  
If a base register value, an index register value and a displacement value are given in the case of operand access, these values are inputted to an arithmetic unit to generate a correctly...
6983347 Dynamically managing saved processor soft states  
A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process...
6976129 Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture  
A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment,...
6963823 Programmatic design space exploration through validity filtering and quality filtering  
Design spaces for systems, including hierarchical systems, are programmatically validity filtered and quality filtered to produce validity sets and quality sets, reducing the number of designs to...
6963962 Memory system for supporting multiple parallel accesses at very high frequencies  
A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a...
6963964 Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses  
In a computer processor, multiple partially translated real addresses for a pipelined operation are compared with the real addresses of one or more other operations in the pipeline to detect an...
6934827 Method and apparatus for avoiding cache line collisions between an object and corresponding object table entries  
One embodiment of the present invention provides a system that facilitates avoiding collisions between cache lines containing objects and cache lines containing corresponding object table entries....
6925636 Method and apparatus for refining an alias set of address taken variables  
A method, apparatus and article of manufacture for performing alias refinement is disclosed. Initially, a determination is made as to whether a load of an address exists for a variable in an...
6925464 Method and system for performing inserts and lookups in memory  
A method and system for performing inserts and lookups in fully associative sections of memory is provided. The system includes a differentiating register to store information that differentiates...
6907505 Immediately available, statically allocated, full-logical-unit copy with a transient, snapshot-copy-like intermediate stage  
A hybrid LUN copy operation that ultimately produces a full LUN copy, but involves a transient snapshot-copy-like intermediate stage. In one embodiment, a statically pre-allocated copy LUN is...
6895492 Method of and apparatus for performing two-layer address translation  
A higher TLB that stores TLB data required for translating a virtual address into a physical address. A higher address translator performs address translation based on the TLB data according to an...
6854048 Speculative execution control with programmable indicator and deactivation of multiaccess recovery mechanism  
Mechanisms and techniques operate in a computerized device to enable or disable speculative execution of instructions such as load instructions on one or more processors in the computerized device....
6823434 System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state  
The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries...
6754798 Method and an apparatus for volume creation in the presence of multiple aggregators  
A method and apparatus to dynamically order features and manage features, especially aggregators, during creation of a logical volume is provided. The method and apparatus make use of a...
Matches 1 - 50 out of 167 1 2 3 4 >