|
Match
|
Document |
Document Title |
|
|
7617381 |
Demand paging apparatus and method for embedded system
A demand paging apparatus and a method for an embedded system are provided. The demand paging apparatus includes a nonvolatile storage device, a physical memory, a demand paging window, and a...
|
|
|
7610454 |
Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses
A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique...
|
|
|
7603026 |
Information processing method and information processing apparatus
This invention provides an information processing method and apparatus, which can set all extent sizes of data divisionally recorded on a disk to be equal to or larger than the minimum recording...
|
|
|
7594094 |
Move data facility with optional specifications
A move data facility is provided that enables optional specifications to be indicated to flexibly control the move operation. Data may be moved from any address space to any other address space...
|
|
|
7590820 |
Efficient algorithm for multiple page size support in IPF long format VHPT
A machine-accessible medium may contain program instructions that, when executed by a processor, may cause the processor to perform at least one operation including searching a virtual hash page...
|
|
|
7577764 |
Method, system, and computer program product for virtual adapter destruction on a physical adapter that supports virtual adapters
A method, computer program product, and distributed data processing system for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter...
|
|
|
7562204 |
Identifying and relocating relocatable kernel memory allocations in kernel non-relocatable memory
A method for identifying relocatable kernel memory allocations in kernel non-relocatable memory is described. In this method, a physical address hardware mapping entry (PA HME) for each process...
|
|
|
7562179 |
Maintaining processor resources during architectural events
In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address...
|
|
|
7555628 |
Synchronizing a translation lookaside buffer to an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
|
|
|
7552308 |
Method and apparatus for temporary mapping of executable program segments
A computer implemented method, data processing system, and computer usable code are provided for managing memory use for program segments in an executable program. The process copies a set of...
|
|
|
7552255 |
Dynamically partitioning pipeline resources
In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing...
|
|
|
7552254 |
Associating address space identifiers with active contexts
In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space...
|
|
|
7543084 |
Method for destroying virtual resources in a logically partitioned data processing system
A method for directly destroying one or more virtual resources that reside within a physical adapter and that are associated with a virtual host. Specifically, the present invention is directed to...
|
|
|
7536530 |
Method and apparatus for determining a dynamic random access memory page management implementation
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the...
|
|
|
7529880 |
Address mapping table and method of storing mapping data in the same
A run level address mapping table and related method provides for storing address mapping data, which maps logical addresses to physical addresses in a flash memory using a flash translation layer....
|
|
|
7523291 |
System and method for testing for memory address aliasing errors
Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by...
|
|
|
7523189 |
Methods and computer readable media for generating displays of user-defined blocks of networking addresses
Methods and computer readable media for generating displays of user-defined blocks of networking addresses on a map of an associated address space are provided. Each block of networking addresses...
|
|
|
7516294 |
Logical partitioning method for storage system
When a static logical partition is set in a storage system, wasted resources are generated depending on the load state of the logical partition. Thus, after a logical partition is created, the...
|
|
|
7509473 |
Segmented storage system mapping
A system for mapping between logical addresses and storage units of a plurality of storage volumes which comprise a storage system. For each volume, logical addresses are mapped to storage units...
|
|
|
7496712 |
Proximity communication-based off-chip cache memory architectures
A proximity interconnect module includes a plurality of off-chip cache memories. Either disposed external to the proximity interconnect module or on the proximity interconnect module are a...
|
|
|
7490282 |
Method and apparatus of turbo encoder
Briefly, an apparatus, a method and a wireless communication device are provided. The wireless communication device includes a turbo encoder to generate an encoded data block and a transmitter to...
|
|
|
7487303 |
Flash memory device and associated data merge method
A memory system comprises a flash memory and a controller comprising a control logic circuit and a working memory storing a flash translation layer. The memory system performs a merge operation by...
|
|
|
7484073 |
Tagged translation lookaside buffers in a hypervisor computing environment
Tagged translation lookaside buffer consistency is enabled in the presence of a hypervisor of a virtual machine computing environment, in which multiple processes of multiple logical processors of...
|
|
|
7480775 |
Method and apparatus for block-oriented memory management provided in smart card controllers
A method for memory management in smart card controllers by writing of data into a data space in a persistent memory is described. In order to save memory space the persistent memory is split into...
|
|
|
7480742 |
Method for virtual adapter destruction on a physical adapter that supports virtual adapters
A method for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter is provided. A mechanism is provided for directly destroying the...
|
|
|
7480684 |
Method and system for object allocation using fill counts
A method for locating a root block in file system metadata, includes traversing the file system metadata to locate a leaf block, wherein the leaf block comprises a plurality of root blocks and at...
|
|
|
7467284 |
Method and system of externalising/internalising data record that allow processing of part or all of the record
A method of external data storage in a system including a primary processing device, having a processor and a primary data storage unit, adapted to run application programs for processing active...
|
|
|
7464249 |
System and method for alias mapping of address space
Mapping of address space by providing real storage including first and second address spaces. The second address space is smaller than and contained within the first address space. Provided within...
|
|
|
7464198 |
System on a chip and a method for programming a DMA controller in a system on a chip
A method is provided for programming a DMA controller in a system on a chip. According to the method, a memory management unit translates a programming virtual address into a programming physical...
|
|
|
7461198 |
System and method for configuration and management of flash memory
A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a...
|
|
|
7461191 |
Segmented on-chip memory and requester arbitration
A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable...
|
|
|
7454591 |
Storage system control method, storage system, and storage apparatus storing information relating a first logical unit number (LUN) used to access a volume by a host computer and a second LUN used to access the volume by another storage system with remote copy procedure
A method controls a storage system including a first storage apparatus including a first storage volume to store data therein, a second storage apparatus including a second storage volume to store...
|
|
|
7444637 |
Systems and methods for scheduling coprocessor resources in a computing system
Systems and methods for scheduling coprocessing resources in a computing system are provided without redesigning the coprocessor. In various embodiments, a system of preemptive multitasking is...
|
|
|
7444480 |
Processor, memory device, computer system, and method for transferring data
A processor connected to a memory device includes a random number generator that generates random numbers identical to random numbers generated in the memory device; an XOR logic unit that performs...
|
|
|
7441090 |
System and method for updating data sectors in a non-volatile memory using logical block addressing
A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of...
|
|
|
7437546 |
Multiple, cooperating operating systems (OS) platform system and method
Embodiments of a multi-processor platform including multiple, cooperating operating systems are described. Multiple operating systems, each of which may be of a different type or nature, run on...
|
|
|
7430202 |
System and method of tributary time-space switching
A tributary time-space switch and a method of switching are provided having low memory requirements. The switch includes a number of inputs and outputs. Each of the inputs receives an input data...
|
|
|
7428620 |
Method for switching data library managers
A device, method, and system for switching library managers of a data library while maintaining data library storage devices online. A library manager accepts and executes data transaction commands...
|
|
|
7428573 |
Transaction accelerator for client-server communication systems
In a network having transaction acceleration, for an accelerated transaction, a client directs a request to a client-side transaction handler that forwards the request to a server-side transaction...
|
|
|
7426625 |
Data processing system and computer program product for support of system memory addresses with holes
A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating...
|
|
|
7421564 |
Incrementing successive write operations to a plurality of memory devices
A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores...
|
|
|
7421533 |
Method to manage memory in a platform with virtual machines
An embodiment of the present invention enables the virtualizing of virtual memory in a virtual machine environment within a virtual machine monitor (VMM). Memory required for direct memory access...
|
|
|
7418572 |
Pretranslating input/output buffers in environments with multiple page sizes
Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports...
|
|
|
7418570 |
Logical unit number increasing device, and logical unit number increasing method
According to an embodiment, virtual logical units are each provided with correlative data between a virtual logical unit number and a real logical unit number. In response to an access request...
|
|
|
7409487 |
Virtualization system for computers that use address space indentifiers
A virtual computer system including multiple virtual machines (VMs) is implemented in a physical computer system that uses address space identifiers (ASIDs). Each VM includes a virtual translation...
|
|
|
7406581 |
Speculative instruction load control
A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address...
|
|
|
7404063 |
Reclaiming the PCI memory range with minimal memory loss in IA-32 platforms
A method for configuring resources in IA-32 computers enables the PCI memory address range to be reclaimed with minimal loss of available physical memory. The BIOS establishes a remap window at the...
|
|
|
7404055 |
Memory transfer with early access to critical portion
In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred...
|
|
|
7395278 |
Transaction consistent copy-on-write database
A database view of a database is created which provides a transaction-consistent view of an existing database at a previous time. Each database view contains all the information needed to, along...
|
|
|
7394884 |
Synchronizing method
To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the...
|