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6880022 Transparent memory address remapping  
A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is...
6880062 Data mover mechanism to achieve SAN RAID at wire speed  
A Virtual Storage Server is provided for transferring data between a source storage device and one or more destination storage devices. A write command is issued to the one or more destinations...
6874057 Method and apparatus for cache space allocation  
A method and apparatus are disclosed for allocating a section of a cache memory to one or more tasks. A set index value that identifies a corresponding set in the cache memory is transformed to a...
6874070 System and method for memory interleaving using cell map with entry grouping for higher-way interleaving  
A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a...
6874004 Method and system for detecting cross linked files  
A method for detecting and correcting cross-linked files while accessing data on a storage media. Each file includes control file information that defines a plurality of blocks on storage media...
6874056 Method and apparatus for reducing cache thrashing  
A method and apparatus are disclosed for adaptively decreasing cache trashing in a cache memory device. Cache performance is improved by automatically detecting thrashing of a set and then...
6865646 Segmented distributed memory module cache  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6865659 Using short references to access program elements in a large address space  
One embodiment of the present invention provides a system that accesses a desired element during execution of a program. During operation, the system receives a reference to the desired element....
6862671 System and method for optimizing establishment of mirrored data  
The present invention is directed to a system and method for optimizing establishment of mirrored data. In an aspect of the present invention, a method of tracking changes to mirrored storage...
6862650 Data processing system and method for managing memory of an interpretive system  
A data processing system and method manage the storage of instructions used in applications developed using an interpretive programming language, such as Java, REXX, BASIC, and the like, when...
6856420 System and method for transferring data within a printer  
A printer is described. The printer includes a CPU, a DMA controller and an internal memory. The CPU and the DMA controller are each connected to a first memory bus. The internal memory is...
6857058 Apparatus to map pages of disparate sizes and associated methods  
A data processing system providing high performance two-dimensional and three-dimensional graphics includes at least one system processor, chipset core logic, a graphics processor, main memory...
6845439 Method and system for accessing an expanded SCB array  
A method for accessing hardware I/O control blocks, which are stored in an hardware I/O control block array, by a parallel SCSI host adapter addresses one page in a plurality of pages of the...
6832303 Method and system for managing an allocation of a portion of a memory  
A method and system are disclosed for managing an allocation of a portion of a memory associated with a central processing unit system that can be selectively coupled to a bus of the central...
6829769 High performance interprocess communication  
Methods, systems, and computer program products for high-performance interprocess communication. Each process dynamically identifies routines responsible for managing communication received from...
6826582 Method and system for using file systems for content management  
A file system and method serves to create and manage content. The file system includes at least one directory having at least one file containing data, but about which at least one file has no...
6816929 Data transfer control method and controller for universal serial bus interface  
A USB device controller is applied to a peripheral device that performs data communications with a host by using a transmission endpoint and a reception endpoint via a USB interface. Herein, a USB...
6813684 Disk drive system and method for controlling a cache memory  
Disclosed is a disk system for controlling divided areas of a cache memory. Identification information that denotes whether data to be accessed is user data or meta data is added to each I/O...
6813699 Speculative address translation for processor using segmentation and optional paging  
An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a...
6807616 Memory address checking in a proccesor that support both a segmented and a unsegmented address space  
A processor supports several operating modes. In at least one of the operating modes, a segmented address space is used. In at least one other operating mode, an unsegmented address space is used....
6807615 Apparatus and method for providing a cyclic buffer using logical blocks  
An apparatus and method for creating and maintaining a cyclic or circular buffer are implemented using logical blocks corresponding to the physical blocks of the buffer. The logical blocks are...
6807618 Address translation  
The description includes techniques of data storage address translation. The techniques can include receiving a first address in a first address space, traversing a trie based on the first...
6804746 Method and system for optimizing data storage and retrieval by an audio/video file system using hierarchical file allocation table  
A system for optimizing data storage and retrieval by an audio/video system using a number of different tables is disclosed. According to one aspect of the system, the system includes two...
6804671 Pluggable tablespaces for database systems  
A pluggable tablespace is enabled by logically partitioning a database into a set of tablespaces and storing all of the tablespaces disk pointers in tablespace-relative format. A pluggable set of...
6795907 Relocation table for use in memory management  
The present invention, in various embodiments, provides techniques for managing memory in computer systems. In one embodiment, each memory page is divided into relocation blocks located at various...
6782466 Arrangement and method for accessing data in a virtual memory arrangement  
A memory access approach optimizes memory address mapping for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is...
6782464 Mapping a logical address to a plurality on non-logical addresses  
Communication between different entities of a computing environment is facilitated by an address mapping capability. Messages are sent between the entities to have desired tasks performed. Instead...
6782467 Method and apparatus for fast limited core area access and cross-port word size multiplication in synchronous multiport memories  
An apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state...
6772274 Flash memory system and method implementing LBA to PBA correlation within flash memory array  
A flash memory system is designed to reduce inefficiencies associated with keeping track of logical block address (LBA) to physical block address (PBA) correlation or mappmg—each logical block...
6766435 Processor with a general register set that includes address translation registers  
A processor having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation...
6763441 System and method for using ancillary processors and storage to speed time critical data capture  
A method for using ancillary processors and memory to speed critical data capture includes building a list memory address ranges associated with a secondary partition. The memory address ranges...
6760795 Data queue system  
A data queue system comprises plural memory blocks defined in memory, and a queue which comprises a number of memory blocks each including a link to the following block in the data queue. A queue...
6757802 Method for memory heap and buddy system management for service aware networks  
A computer system for allocating memory comprises a central processing unit (CPU) for controlling said system, a local memory for said CPU, means for allocating a plurality of memory blocks to...
6738889 Apparatus and method for providing simultaneous local and global addressing with hardware address translation  
An apparatus and method provide simultaneous local and global addressing capabilities. A global address space is defined that may be accessed by all processes. In addition, each process has a...
6732192 Disc recording scheme for enabling quick access to disc data  
A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical...
6725289 Transparent address remapping for high-speed I/O  
A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory...
6718352 Methods and apparatus for managing a data set stored on a data storage device  
The invention is directed to techniques for managing a data set stored on a host computer that is in communication with a data storage assembly. A data manager on a host computer copies the data...
6711227 Synchronizing method and apparatus  
To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the...
6701422 Memory control system with incrementer for generating speculative addresses  
A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to...
6691118 Context management system for modular software architecture  
A context management system manages both thread-local data and free-thread data in a flexible modular architecture. Thread data is segmented into an ordinal workspace structure. In a free thread...
6687805 Method and system for logical-object-to-physical-location translation and physical separation of logical objects  
A method and system for providing to a human user or high-level application program a functional interface for translating the names of logical objects into physical mappings of logical objects to...
6684313 Managing storage contention in automated storage systems  
An automated process of assigning storage resources to logical units (“LU's”) is informed of contention avoidance, in order to yield reduced contention. LU's are defined and assigned to logical...
6681310 Storage management system having common volume manager  
A storage management system in which a plurality of volume providers maps logical storage volumes onto one or more storage devices within a stand-alone computer or within a storage network. A...
6681224 Method and device for sorting data, and a computer product  
The sorting device comprises a distribution monitoring and cell splitting section which analyzes a distribution of a sort target data group consisting sort target data and obtains an appearance...
6681311 Translation lookaside buffer that caches memory type information  
A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base...
6671786 System and method for mirroring memory with restricted access to main physical mirrored memory  
The present invention includes a method of mirroring memory that reduces the down time for copying information from one physical memory subsystem to a redundant physical memory subsystem by...
6665785 System and method for automating page space optimization  
An optimizing tool optimizes a computer system's page space by basing the page size on the amount of real memory in the computer system. The optimization tool determines the amount of real memory...
6651132 System and method for emulating the operation of a translation look-aside buffer  
A method for tracking the changes to the emulated page tables of a host computer system is disclosed in which each memory location accessed by the guest computer system is placed on one of several...
6640252 Apparatus and method for physically and logically packaging and distributing items in a distributed environment  
An apparatus and method for creating packages and for transferring packages between computer systems provides a graphical user interface that allows a user to define various attributes for a...
6640296 Data processing method and device for parallel stride access  
A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable...