Matches 401 - 450 out of 487 < 1 2 3 4 5 6 7 8 9 10 >
Match Document Document Title
5706461 Method and apparatus for implementing virtual memory having multiple selected page sizes  
A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the...
5699542 Address space manipulation in a processor  
A method and apparatus for configuring the address space of a computer is described. According to the present invention, a computer system has a full address space and includes at least one base...
5692167 Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor  
An apparatus and method for improving the performance of pipelined computer processors which have segment bits for specifying the operand size, the address size for memory reference, and the stack...
5687343 Product for global updating modified data object represented in concatenated multiple virtual space by segment mapping  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5684974 Method and apparatus for controlling reconfiguration of storage-device memory areas  
An apparatus and method for controlling the reconfiguration of the physical storage area in a real storage device employed by an information processing system. The invention includes an address...
5684995 Segment division management system  
One physical segment 30 is divided into a plurality of fixed-length logic segments 31, where a logic segment management table 22 for management each logic segment 31 is provided. In registering a...
5684993 Segregation of thread-specific information from shared task information  
A multi-processor system includes memory and at least two central processing units (CPUs) that may execute different threads of computation of a same task at the same time. CPU-specific data is...
5664139 Method and a computer system for allocating and mapping frame buffers into expanded memory  
A video driver in a computer system is used to map a large video frame buffer into the logical address space above physical memory while the computer system is operating in WINDOWS STANDARD mode....
5664160 Computer program product for simulating a contiguous addressable data space  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5664144 System and method for FBA formatted disk mapping and variable-length CKD formatted data record retrieval  
An apparatus and method for disk mapping and data retrieval includes a data storage medium on which has been stored a plurality of data records. Each record includes at least a record...
5652854 Method and apparatus for mapping page table trees into virtual address space for address translation  
Techniques used in a virtual memory system for mapping the page table for a process onto the process's virtual address space. The mappings make it possible for the virtual memory manager to compute...
5649141 Multiprocessor system for locally managing address translation table  
An address translation technique used in a multiprocessor system is disclosed. In a multiprocessor system for connecting a plurality of clusters with each other via a network, each of these...
5649142 Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault  
A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and...
5644747 Page mode access memory controller including plural address latches and a comparator  
A memory controller for a computer system having a processor and dynamic random access memories (DRAMs) which are grouped into banks, and having multiple latches associated respectively with the...
5640527 Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states  
An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory...
5628023 Virtual storage computer system having methods and apparatus for providing token-controlled access to protected pages of memory via a token-accessible view  
A virtual storage computer system having token controlled storage protection. The computer system includes a processor, a real storage, and a virtual storage containing a user space and a system...
5619670 Address decoder with small circuit scale and address area expansion capability  
An address decoder has a plurality of address comparator circuits for respective address areas, each comparator circuit including a base address register, a mask register, an AND gate, and a...
5611064 Virtual memory system  
In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address...
5603011 Selective shadowing and paging in computer memory systems  
Principal data (e.g. frequently accessed data such as video BIOS program information and a principal font set) and secondary data (e.g. secondary font sets) are permanently stored in a slow memory...
5602995 Method and apparatus for buffering data within stations of a communication network with mapping of packet numbers to buffer's physical addresses  
Method and apparatus for buffering data packets in a data communication controller environment. In general, the communication controller is interfaceable with a host processor and includes a...
5598553 Program watchpoint checking using paging with sub-page validity  
Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment...
5594881 System for updating modified pages of data object represented in concatenated multiple virtual address spaces  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5590298 Method of restoring and updating records in a disk cache system during disk drive idle time using start and end addresses  
A method of restoring write data in a disk cache system includes the steps of providing a host, a disk drive having a plurality of tracks including a plurality of records, a cache memory, a...
5590301 Address transformation in a cluster computer system  
In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass...
5584015 Buffer memory management method, recording medium, and computer system incorporating same  
A buffer memory management method for a buffer memory consisting of a set (14) of buffers (15), using a list of buffers arranged by order of least recent use (LRU). The method comprises, when a...
5579499 Product for representing data object in concatenated multiple virtual address spaces with combined requests for segment mapping  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5577243 Reallocation of returned memory blocks sorted in predetermined sizes and addressed by pointer addresses in a free memory list  
In an electronic data processing apparatus blocks of returned memory 3 are linked by address pointers starting with a pointer in a table 1. Each pointer in the table 1 points to memory of within a...
5577221 Method and device for expanding ROM capacity  
An expandable ROM module adapted for use with an existing ROM interface having a predetermined number of address lines to provide an expanded memory array of variable size. The expanded memory is...
5574877 TLB with two physical pages per virtual tag  
A TLB which has at least two page frame numbers (PFN) associated with each tag (Virtual Page Number) is provided. Thus, a match will produce two possible physical page frame numbers. The selection...
5568415 Content addressable memory having a pair of memory cells storing don't care states for address translation  
A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't...
5564023 Method for accessing a sequencer control block by a host adapter integrated circuit  
A busy targets table is created in a memory that can be either internal or external to a SCSI host adapter. Each entry in the table initially is set to a predetermined value. Prior to starting...
5564031 Dynamic allocation of registers to procedures in a digital computer  
In a digital computer, a circular queue of registers in a register file are allocated as temporary local storage for procedures rather than using the known caller/callee save convention in order to...
5561778 System for representing data object in concatenated multiple virtual address spaces with combined requests for segment mapping  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5544293 Buffer storage system and method using page designating address and intra-page address and detecting valid data  
A buffer storage system and method using a page designating address and an intra-page address for information processing according to a logical address is provided. The buffer storage system...
5537652 Data file directory system and method for writing data file directory information  
A data storage medium having the ability to recover from media errors includes a directory located at any desired region of a data storage area with redundant directory pointers at reserved...
5526504 Variable page size translation lookaside buffer  
A set associative translation lookaside buffer (TLB) that supports variable sized pages without requiring the use of a separate block TLB. The TLB includes a hashing circuit that creates an index...
5504872 Address translation register control device in a multiprocessor system  
A multiprocessor system address translation register control device that creates a directory for the handling of various address translation registers, wherein the directory retains processor data...
5493661 Method and system for providing a program call to a dispatchable unit's base space  
A method and system for providing a PROGRAM CALL to a dispatchable unit's base space is described herein. A program call to a dispatchable unit's (PC to DU) base space bit is added to each...
5481688 Information processing system having an address translation table loaded with main/expanded memory presence bits  
An information processing system has a main memory unit, an expanded memory unit, and an instruction processing unit producing a virtual address. An address translation table, namely, a page table...
5479639 Computer system with a paged non-volatile memory  
A computer system wherein a paging technique is used to expand the useable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment...
5479635 Memory device including DRAMs for high-speed accessing  
A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each...
5475827 Dynamic look-aside table for multiple size pages  
A dynamic address translation (DAT) mechanism which supports virtual memory pages of different sizes with minimal hardware and design impact. The dynamic look-aside table (DLAT) is modified to...
5461718 System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory  
A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system...
5455944 Method for managing logging and locking of page free space information in a transaction processing system  
Database files containing records include pages called free space inventory pages (FSIPs) describing field space information relating to data pages. In a transaction processing system, the...
5455920 Multiprocessor system having offset address setting  
A multiprocessor system includes the first microcomputer (1) having the first memory (4); the second microcomputer (9) having the second memory (12), the dual port third memory (14), and an offset...
5455934 Fault tolerant hard disk array controller  
The disk array control system is a fault tolerant controller for arrays of hard disk drives. With the controller as a front end, an array of hard disk drives would appear as a single drive to a...
5442802 Asynchronous co-processor data mover method and means  
Virtual addressing is available to a co-processor to asynchronously control the movement of multiple page units of data between different locations in the same or a different media, e.g. main store...
5432917 Tabulation of multi-bit vector history  
A multi-bit SP-Vector is created to record the history of each page of a process. Each time an ager scans the accessed/not accessed bit flag of the page tables entires, the SP-Vector is updated to...
5430856 Data processing system simultaneously performing plural translations of virtual addresses having different page sizes  
A data processing system which is capable of performing simultaneously multiple address translation of logical addresses of different page sizes into corresponding physical addresses. The system...
5428759 Associative memory system having segment and page descriptor content-addressable memories  
An associative memory system for logical addressing of memory segments using paged memory. The physical address of a targeted data word can be generated in one machine cycle if the segment logical...
Matches 401 - 450 out of 487 < 1 2 3 4 5 6 7 8 9 10 >