|
Match
|
Document |
Document Title |
|
|
6760795 |
Data queue system
A data queue system comprises plural memory blocks defined in memory, and a queue which comprises a number of memory blocks each including a link to the following block in the data queue. A queue...
|
|
|
6757802 |
Method for memory heap and buddy system management for service aware networks
A computer system for allocating memory comprises a central processing unit (CPU) for controlling said system, a local memory for said CPU, means for allocating a plurality of memory blocks to...
|
|
|
6738889 |
Apparatus and method for providing simultaneous local and global addressing with hardware address translation
An apparatus and method provide simultaneous local and global addressing capabilities. A global address space is defined that may be accessed by all processes. In addition, each process has a local...
|
|
|
6732192 |
Disc recording scheme for enabling quick access to disc data
A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical...
|
|
|
6725289 |
Transparent address remapping for high-speed I/O
A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region....
|
|
|
6718352 |
Methods and apparatus for managing a data set stored on a data storage device
The invention is directed to techniques for managing a data set stored on a host computer that is in communication with a data storage assembly. A data manager on a host computer copies the data...
|
|
|
6711227 |
Synchronizing method and apparatus
To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the...
|
|
|
6701422 |
Memory control system with incrementer for generating speculative addresses
A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to...
|
|
|
6691118 |
Context management system for modular software architecture
A context management system manages both thread-local data and free-thread data in a flexible modular architecture. Thread data is segmented into an ordinal workspace structure. In a free thread...
|
|
|
6687805 |
Method and system for logical-object-to-physical-location translation and physical separation of logical objects
A method and system for providing to a human user or high-level application program a functional interface for translating the names of logical objects into physical mappings of logical objects to...
|
|
|
6684313 |
Managing storage contention in automated storage systems
An automated process of assigning storage resources to logical units (“LU's”) is informed of contention avoidance, in order to yield reduced contention. LU's are defined and assigned to logical...
|
|
|
6681310 |
Storage management system having common volume manager
A storage management system in which a plurality of volume providers maps logical storage volumes onto one or more storage devices within a stand-alone computer or within a storage network. A...
|
|
|
6681311 |
Translation lookaside buffer that caches memory type information
A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base...
|
|
|
6681224 |
Method and device for sorting data, and a computer product
The sorting device comprises a distribution monitoring and cell splitting section which analyzes a distribution of a sort target data group consisting sort target data and obtains an appearance...
|
|
|
6671786 |
System and method for mirroring memory with restricted access to main physical mirrored memory
The present invention includes a method of mirroring memory that reduces the down time for copying information from one physical memory subsystem to a redundant physical memory subsystem by...
|
|
|
6665785 |
System and method for automating page space optimization
An optimizing tool optimizes a computer system's page space by basing the page size on the amount of real memory in the computer system. The optimization tool determines the amount of real memory...
|
|
|
6651132 |
System and method for emulating the operation of a translation look-aside buffer
A method for tracking the changes to the emulated page tables of a host computer system is disclosed in which each memory location accessed by the guest computer system is placed on one of several...
|
|
|
6640296 |
Data processing method and device for parallel stride access
A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable...
|
|
|
6640252 |
Apparatus and method for physically and logically packaging and distributing items in a distributed environment
An apparatus and method for creating packages and for transferring packages between computer systems provides a graphical user interface that allows a user to define various attributes for a...
|
|
|
6636925 |
Bus interface circuit preparation apparatus and recording medium
An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware...
|
|
|
6629189 |
Method and apparatus for managing target devices in a multi-path computer system
A method and apparatus for managing at least one logical volume in a computer system that includes a processor, a storage system, and a plurality of paths coupling the processor to the storage...
|
|
|
6629187 |
Cache memory controlled by system address properties
A digital system is provided with a microprocessor ( 100 ), a cache ( 120 ) and various memory and devices ( 140 a -140 n ). Signals to control certain cache memory modes are provided by a physical...
|
|
|
6629199 |
DIGITAL DATA STORAGE SYSTEM INCLUDING DIRECTORY FOR EFFICIENTLY PROVIDING FORMATTING INFORMATION FOR STORED RECORDS AND UTILIZATION OF A CHECK VALUE FOR VERIFYING THAT A RECORD IS FROM A PARTICULAR STORAGE LOCATION
A digital data storage system in the form of a mass storage subsystem in which information is stored on one or more disk storage units, with a storage element constituting a track on a disk storage...
|
|
|
6625713 |
Memory controller and method for managing a logical/physical address control table
A memory controller for reading data stored in a nonvolatile memory that includes a number of erasable blocks containing a number of pages. A logical/physical address control table stored in a...
|
|
|
6625708 |
Method and apparatus for dynamically defining line buffer configurations
A method and apparatus of defining a line buffer configuration in a memory is disclosed. In one embodiment, the method and apparatus receives input data information and mode information, proceeds...
|
|
|
6625712 |
Memory management table producing method and memory device
The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information...
|
|
|
6622230 |
Multi-set block erase
A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block...
|
|
|
6622231 |
Method and apparatus for paging data and attributes including an atomic attribute
A digital data processing apparatus configured to selectively transfer data between a primary data storage element and an associated data file on a secondary data storage element. The apparatus...
|
|
|
6606698 |
Apparatus and method for managing data storage
A data storage managing apparatus is described which translates a host Input/Output (I/O) request into a standard form. Thus, I/O requests sent by different hosts using different protocols are...
|
|
|
6604186 |
Method for dynamically adjusting memory system paging policy
A method and apparatus of dynamically adjusting a memory system's existing paging policy is disclosed. In one embodiment, the method for dynamically adjusting the paging policy generates a select...
|
|
|
6604184 |
Virtual memory mapping using region-based page tables
The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual...
|
|
|
6604187 |
Providing global translations with address space numbers
A processor provides a register for storing an address space number (ASN). Operating system software may assign different ASNs to different processes. The processor may include a TLB to cache...
|
|
|
6594751 |
Method and apparatus for pointer relocation optimization for virtual memory mapping and transaction management in a database system
There is provided an apparatus and a method for virtual memory mapping and transaction management for an object-oriented data base system having at least one permanent storage means for storing...
|
|
|
6593932 |
System for implementing a graphic address remapping table as a virtual register file in system memory
A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references a...
|
|
|
6591328 |
Non-volatile memory storing address control table data formed of logical addresses and physical addresses
A non-volatile memory including a logical/physical address control table for controlling data recorded discretely in the non-volatile memory composed of a plurality of blocks each serving as a data...
|
|
|
6587915 |
Flash memory having data blocks, spare blocks, a map block and a header block and a method for controlling the same
A flash memory and a method for controlling the same are disclosed. The flash memory has units, each of which includes a plurality of data blocks for writing data; a plurality of spare blocks...
|
|
|
6581132 |
Flash memory system including a memory manager for managing data
A flash memory system of the present invention comprises a memory manager for managing data transmission/reception between a host computer and a flash memory, said memory manager having an address...
|
|
|
6581130 |
Dynamic remapping of address registers for address translation between multiple busses
Address translation between various peripheral bus interfaces is provided through a bus interface device. Specifically, the bus interface device translates incoming transactions from a source bus...
|
|
|
6578129 |
Optimized virtual memory management for dynamic data types
The present invention proposes effective solutions for the design of Virtual Memory Management for applications with dynamic data types in an embedded (HW or SW) processor context. A structured...
|
|
|
6578128 |
Address management for a shared memory region on a multi-processor controller board
A system having a memory with a plurality of contiguous processor memory regions and a plurality of processors. Each one of such processors is associated with a corresponding one of the processor...
|
|
|
6574721 |
Apparatus and method for providing simultaneous local and global addressing using software to distinguish between local and global addresses
An apparatus and method provide simultaneous local and global addressing capabilities in a computer system. A global address space is defined that may be accessed by all processes. In addition,...
|
|
|
6571330 |
Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor
A processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64...
|
|
|
6553460 |
Microprocessor having improved memory management unit and cache memory
Methods of managing a cache memory system in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in...
|
|
|
6553478 |
Computer memory access
A memory for a computer system that includes a plurality of memory banks which provide an interleaved memory region as well as X and Y memory regions. Each memory access address includes a most...
|
|
|
6553475 |
Memory system with address conversion based on inherent performance condition
A memory system includes a memory including a plurality of memory regions operating based on an identical principle; and an address conversion device for converting a logical address into a...
|
|
|
6549901 |
Using transportable tablespaces for hosting data of multiple users
Provided are mechanisms that may be used to support efficient exportation of user data stored in a database system. According to an aspect of the present invention, a database system is configured...
|
|
|
6549996 |
Scalable multiple address space server
A method and apparatus are provided for managing the amount of memory available to processes within the computer system. Additional virtual address spaces are dynamically created to make more...
|
|
|
6542978 |
Externally identifiable descriptor for standard memory allocation interface
The invention noninvasively provides information relating to memory space allocation. Memory space allocation information is maintained in a location that is known or identifiable outside of the...
|
|
|
6529996 |
Network attached virtual tape data storage subsystem
The network attached virtual tape storage subsystem interconnects a plurality of tape devices with a plurality of data processors via a high bandwidth switching network to implement a virtual,...
|
|
|
6526473 |
Memory module system for controlling data input and output by connecting selected memory modules to a data line
A memory module system for connecting only selected memory modules to a data line to control data input and output is disclosed. The memory module system has a multiplicity of memory modules for...
|