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5598553 Program watchpoint checking using paging with sub-page validity  
Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment...
5594881 System for updating modified pages of data object represented in concatenated multiple virtual address spaces  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5590298 Method of restoring and updating records in a disk cache system during disk drive idle time using start and end addresses  
A method of restoring write data in a disk cache system includes the steps of providing a host, a disk drive having a plurality of tracks including a plurality of records, a cache memory, a...
5590301 Address transformation in a cluster computer system  
In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass...
5584015 Buffer memory management method, recording medium, and computer system incorporating same  
A buffer memory management method for a buffer memory consisting of a set (14) of buffers (15), using a list of buffers arranged by order of least recent use (LRU). The method comprises, when a...
5579499 Product for representing data object in concatenated multiple virtual address spaces with combined requests for segment mapping  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5577243 Reallocation of returned memory blocks sorted in predetermined sizes and addressed by pointer addresses in a free memory list  
In an electronic data processing apparatus blocks of returned memory 3 are linked by address pointers starting with a pointer in a table 1. Each pointer in the table 1 points to memory of within a...
5577221 Method and device for expanding ROM capacity  
An expandable ROM module adapted for use with an existing ROM interface having a predetermined number of address lines to provide an expanded memory array of variable size. The expanded memory is...
5574877 TLB with two physical pages per virtual tag  
A TLB which has at least two page frame numbers (PFN) associated with each tag (Virtual Page Number) is provided. Thus, a match will produce two possible physical page frame numbers. The selection...
5568415 Content addressable memory having a pair of memory cells storing don't care states for address translation  
A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't...
5564031 Dynamic allocation of registers to procedures in a digital computer  
In a digital computer, a circular queue of registers in a register file are allocated as temporary local storage for procedures rather than using the known caller/callee save convention in order...
5564023 Method for accessing a sequencer control block by a host adapter integrated circuit  
A busy targets table is created in a memory that can be either internal or external to a SCSI host adapter. Each entry in the table initially is set to a predetermined value. Prior to starting...
5561778 System for representing data object in concatenated multiple virtual address spaces with combined requests for segment mapping  
Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data...
5544293 Buffer storage system and method using page designating address and intra-page address and detecting valid data  
A buffer storage system and method using a page designating address and an intra-page address for information processing according to a logical address is provided. The buffer storage system...
5537652 Data file directory system and method for writing data file directory information  
A data storage medium having the ability to recover from media errors includes a directory located at any desired region of a data storage area with redundant directory pointers at reserved...
5526504 Variable page size translation lookaside buffer  
A set associative translation lookaside buffer (TLB) that supports variable sized pages without requiring the use of a separate block TLB. The TLB includes a hashing circuit that creates an index...
5504872 Address translation register control device in a multiprocessor system  
A multiprocessor system address translation register control device that creates a directory for the handling of various address translation registers, wherein the directory retains processor data...
5493661 Method and system for providing a program call to a dispatchable unit's base space  
A method and system for providing a PROGRAM CALL to a dispatchable unit's base space is described herein. A program call to a dispatchable unit's (PC to DU) base space bit is added to each...
5481688 Information processing system having an address translation table loaded with main/expanded memory presence bits  
An information processing system has a main memory unit, an expanded memory unit, and an instruction processing unit producing a virtual address. An address translation table, namely, a page table...
5479635 Memory device including DRAMs for high-speed accessing  
A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each...
5479639 Computer system with a paged non-volatile memory  
A computer system wherein a paging technique is used to expand the useable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment...
5475827 Dynamic look-aside table for multiple size pages  
A dynamic address translation (DAT) mechanism which supports virtual memory pages of different sizes with minimal hardware and design impact. The dynamic look-aside table (DLAT) is modified to...
5461718 System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory  
A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system...
5455920 Multiprocessor system having offset address setting  
A multiprocessor system includes the first microcomputer (1) having the first memory (4); the second microcomputer (9) having the second memory (12), the dual port third memory (14), and an offset...
5455934 Fault tolerant hard disk array controller  
The disk array control system is a fault tolerant controller for arrays of hard disk drives. With the controller as a front end, an array of hard disk drives would appear as a single drive to a...
5455944 Method for managing logging and locking of page free space information in a transaction processing system  
Database files containing records include pages called free space inventory pages (FSIPs) describing field space information relating to data pages. In a transaction processing system, the...
5442802 Asynchronous co-processor data mover method and means  
Virtual addressing is available to a co-processor to asynchronously control the movement of multiple page units of data between different locations in the same or a different media, e.g. main...
5432917 Tabulation of multi-bit vector history  
A multi-bit SP-Vector is created to record the history of each page of a process. Each time an ager scans the accessed/not accessed bit flag of the page tables entires, the SP-Vector is updated to...
5430856 Data processing system simultaneously performing plural translations of virtual addresses having different page sizes  
A data processing system which is capable of performing simultaneously multiple address translation of logical addresses of different page sizes into corresponding physical addresses. The system...
5428759 Associative memory system having segment and page descriptor content-addressable memories  
An associative memory system for logical addressing of memory segments using paged memory. The physical address of a targeted data word can be generated in one machine cycle if the segment logical...
5426752 Method for allocating real pages to virtual pages having different page sizes therefrom  
A method for allocating real pages larger than a conventional size to a plurality of virtual pages of the conventional size in a system including a real storage containing a plurality of real...
5394539 Method and apparatus for rapid data copying using reassigned backing pages  
A data processing system, having virtual addressing capability, has a real storage manager to associate virtual storage locations with real storage by accessing page tables to determine the...
5388242 Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on demand page swapping  
A computer system employs multiple CPUs, all executing the same instruction stream, with multiple, identical memory modules storing duplicates of the same data and accessable by all the CPUs,...
5386522 Dynamic physical address aliasing during program debugging  
The physical memory of a computer may not be directly accessable to the operator during the operation of a program due to the operational requirements of the operating system. Direct access to the...
5375214 Single translation mechanism for virtual storage dynamic address translation with non-uniform page sizes  
A dynamic address translation mechanism uses a single translation look aside buffer (TLB) facility for pages of various sizes. The single TLB is supported by a small amount of special hardware....
5319758 Method for managing multiple virtual storages divided into families  
A multiple virtual storage management method which requests, by a first program allocated to a first virtual space, subordination of the first virtual space to a first one of the space families at...
5282274 Translation of multiple virtual pages upon a TLB miss  
Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and...
5278963 Pretranslation of virtual addresses prior to page crossing  
An address translation mechanism for generating real addresses, within a page. based on stride from a beginning translated address in the page. However, whenever there is a page crossing, an...
5226132 Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system  
Instead of translation from a space address to a segment table origin address (STO) by an ordinary instruction, translation to the STO is done by a space base register modify instruction which...
5155826 Memory paging method and apparatus  
A method and apparatus to operate a paged memory system which uses only a single, predetermined address per page as a memory-mapped address. When the single memory-mapped address is accessed...
5155852 Digital information coding system which evenly distributes valid input data to digital signal processors operating in parallel  
A digital signal processing apparatus which is used for the computation of coding image signals or the like and a motion compensative operation method which uses a digital signal processing...
5129070 Method of using the memory in an information processing system of the virtual addressing type, and apparatus for performing the method  
The method and apparatus for using the memory in an information processing system of the virtual addressing type is characterized in that a first memory domain DX is organized around a logical...
5095420 Method and system for performing virtual address range mapping in a virtual storage data processing system  
A linear data set is mapped to one or more non-main storage virtual data spaces. Portions of this data space are then selectively mapped to a "window" in an address space in which an application...
5058003 Virtual storage dynamic address translation mechanism for multiple-sized pages  
A dynamic address translation mechanism includes a first directory-look-aside-table (DLAT) for 4KB page sizes and a second DLAT for 1MB page sizes. The page size does need not be known prior to...
4992936 Address translation method and apparatus therefor  
In a method and apparatus wherein a logical address of a main storage designated by a program is translated into a real address: an address translation table for each of a plurality of address...
4991082 Virtual storage system and method permitting setting of the boundary between a common area and a private area at a page boundary  
An area boundary between a system common area and a job private area is set at any page boundary independently from a segment boundary, and for the segment (boundary segment) containing the area...
4985828 Method and apparatus for generating a real address multiple virtual address spaces of a storage  
A multiple virtual space control in a multiple virtual storage system having an address translation table used to translate a logical address to a real address, a control register for holding a...
4961134 Method for minimizing locking and reading in a segmented storage space  
A page-accessing method in a segmented tablespace 10 which eliminates unnecessary reading and locking. The tablespace comprises data pages 18 grouped into identically-sized segments 16, each...
4835734 Address translation apparatus  
A virtual space is divided into a plurality of areas of different memory block size, and a plurality of address translation modes are executed using different memory block sizes and based upon a...
4812969 Address translation unit  
An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative...