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6449705 Method and apparatus for improving performance of drive linking through use of hash tables  
A method for routing an input/output request for a particular logical volume. In a preferred embodiment, partitions are assigned to logical volumes, wherein an arbitrary number of partitions can...
6446189 Computer system including a novel address translation mechanism  
A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within...
6446186 Method, apparatus and article of manufacture for mapping physical memory in a virtual address system  
A method, apparatus and article of manufacture are provided for minimizing the number of look-ups in a page table entry (PTE) data structure during mapping of virtual addresses to physical...
6438621 In-memory modification of computer programs  
The present invention provides a facility for performing self-patching of computer code in memory. The facility patches a segment of executable code at runtime under the control of the code...
6434685 Paged memory management system within a run-time environment  
In a paged memory system, memory is allocated as pages and aligned on 2N-byte boundaries that are at least as large as the largest page size. Memory management information about the page is stored...
6430672 Method for performing address mapping using two lookup tables  
A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective...
6427199 Method and apparatus for efficiently transferring data between peripherals in a selective call radio  
A selective call radio (300) includes a memory (100), which in turn includes one or more memory elements; a row and column decoder (110, 112) coupled to the one or more memory elements, an address...
6421770 Buffer memory configuration having a memory between a USB and a CPU  
The buffer memory configuration has a memory disposed between a USB and a central processing unit. The memory can be mapped onto an address space which is exactly half as large as the memory...
6408373 Method and apparatus for pre-validating regions in a virtual addressing scheme  
A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB)...
6405295 Data storage apparatus for efficient utilization of limited cycle memory material  
In the semiconductor memory device relating to the present invention, the memory is divided into a plurality of blocks having a plurality of sectors and stores user data in units of sectors. When...
6401177 Memory system for restructuring a main memory unit in a general-purpose computer  
A memory system has a plurality of memory banks, performs interleaving between the memory banks, and structures a memory by dividing into a plurality of memory blocks which are independently...
6401185 Method and apparatus for accessing paged objects using a fast division technique  
A fast division technique is provided to calculate the address of a slot in a paged object, when the slot is located on a different page than the beginning of the object. The fast division...
6378060 System to implement a cross-bar switch of a broadband processor  
The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in...
6374343 Array indexing with sequential address generator for a multi-dimensional array having fixed address indices  
A method and apparatus for sequentially generating a set of addresses, defined over a plurality of indices, for a multi-dimensional array stored in a memory for the condition where at least one of...
6367002 Apparatus and method for fetching instructions for a program-controlled unit  
An apparatus and a method are distinguished in that an instruction queue is provided which is configured such that when instruction data are written into the instruction queue and/or when...
6363372 Method for selecting unique identifiers within a range  
A method for selecting a next available identifier. A plurality of unique identifiers are assigned, preferably in blocks, to each of a plurality of banks. Within each of the banks, when empty,...
6363473 Simulated memory stack in a stackless environment  
A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before...
6356991 Programmable address translation system  
A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs...
6351807 Data processing system utilizing multiple resister loading for fast domain switching  
A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write...
6349376 Method for decoding addresses using comparison with range previously decoded  
A method for providing the results of an address decode operation involves comparing the address of an address to be decoded with the address range containing an address previously decoded in a...
6349380 Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor  
A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or...
6345241 Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device  
A method and an apparatus for simulation of data in a computing system environment having a controlling program, a main memory, a plurality of hosts, at least one adapter and a queued-direct...
6334173 Combined cache with main memory and a control method thereof  
A combined cache with main memory and a control method thereof, which can be configured with various structures of cache by only adding a minimized control circuit in order to be used as main...
6329985 Method and apparatus for graphically displaying mapping of a logical object  
A method and apparatus for manipulating data in a storage device that is coupled to a host computer. Manipulations that can be performed by the storage device include moving non-contiguous blocks...
6314501 Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory  
A computer system comprises a plurality of processing modules that can be configured into different partitions within the computer system, and a main memory. Each partition operates under the...
6311252 Method and apparatus for moving data between storage levels of a hierarchically arranged data storage system  
A method of moving data between first, second, and third storage levels of a hierarchically arranged data storage system is described. The method includes the steps of dividing address space into...
6308257 Method and apparatus for generating boundary markers for an instruction stream including variable-length instructions  
A method of generating boundary markers, for an instruction stream including variable-length instructions, includes generating a number of sets of potential boundary markers for a predetermined...
6308248 Method and system for allocating memory space using mapping controller, page table and frame numbers  
A method and apparatus of allocating memory space in a main memory of a computer system to a unified memory architecture device. The main memory is associated with a physical address space. A...
6298411 Method and apparatus to share instruction images in a virtual cache  
A method of accessing information in a cache of a multithreaded system comprises providing a virtual address of an instruction to be accessed by a thread. Upon a cache miss, the physical address...
6298437 Method for vectoring pread/pwrite system calls  
A method is provided for I/O data transfer between memory and disk. In one embodiment, an application program generates N data transfer requests. Thereafter, a data transfer list is created that...
6295584 Multiprocessor computer system with memory map translation  
An apparatus and method is disclosed for allowing a multiprocessor computer system with shared memory distributed among multiple nodes to appear like a single-node environment. The single-node...
6292878 Data recorder and method of access to data recorder  
The present invention relates to a data recorder which chronologically records continuous data such as image data without interruption at high speed, a medium which stores the procedure of...
6282626 No stall read access-method for hiding latency in processor memory accesses  
The memory space accessible by a processor is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions are regarded as normal...
6279095 Method and apparatus for omnibus wiring of virtual mapping table entries  
A method and apparatus that operates within a virtual memory system in which portions of the memory system can be "omnibus wired," Omnibus wiring a page guarantees that the page is present in...
6279083 Circuit and method of controlling cache memory  
A memory controller (26) compares the current address and the previous address sent by a microprocessor (12). If the addresses are DRAM addresses and the current row address matches the previous...
6275900 Hybrid NUMA/S-COMA system and method  
A hybrid non-uniform-memory-architecture/simple-cache-only-memory-arc hitecture (NUMA/S-COMA) memory system and method are described useful in association with a computer system having a plurality...
6272052 Block-erase type semiconductor storage device with independent memory groups having sequential logical addresses  
A semiconductor storage device having a plurality of block-erase type non volatile memory chips classifies the memory chips into memory groups of a number equal to twice the number of buffer...
6272612 Process for allocating memory in a multiprocessor data processing system  
The invention relates to a process for allocating physical memory locations in a multiprocessor data processing system comprising a non-uniform access memory unit distributed among a plurality of...
6272503 Tablespace-relative database pointers  
A database containing datafiles is partitioned into a set of tablespaces. Every disk pointer pointing to a data item in a datafile refers to a tablespace-relative file number for the datafile....
6256644 Control system for storing data in accordance with predefined characteristics thereof  
A system is provided for controlling storing databases in nonvolatile storages by a program. The database is composed as a set of records. In the system, a record storing reference table and data...
6233668 Concurrent page tables  
Each processor in a multi-processor system includes a process page-table-base register and a system page-table-base register. Each register identifies a different page frame containing a different...
6233649 Digital signal reproducing method  
A method of reproducing digital signals recorded on a disk having first and second recording surfaces. The digital signals are in the form of a data frame including a lead-in block and n data...
6226733 Address translation mechanism and method in a computer system  
An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed...
6222564 Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controller  
The shared computer system memory is partitioned between system memory and frame buffer memory. The frame buffer is configured as the top-most portion of the shared memory. A virtual memory...
6223247 Disk shaped recording medium and drive apparatus utilizing logical block address conversion and start addresses which increase from inner and outer circumferential sides of the medium  
A disk shaped recording medium, drive apparatus and method for driving a medium divided into at least a recordable area and a reproduction only area, are disclosed. Address conversion is carried...
6216201 Data processing apparatus using paged buffer memory for efficiently processing data of a compact digital disk  
A data processing apparatus of an optical disk drive includes a buffer memory which has a page area divided into a plurality of pages, each page having a predetermined size and containing a main...
6212614 Legacy MIL-STD-1750A software emulator address translation using power PC memory management hardware  
A system and method for implementing the paging and protection attributes, such as block protection and access lock and key functions promulgated in MIL-STD-1750A. The present invention takes...
6212612 System and method for synchronized, multi-channel data management with dynamically configurable routing  
A system and method for multi-channel data management with dynamically configurable routing, having multiple independent container instances or crossbars. The system and method provide dynamically...
6205569 Error recovery using alternate headers in a disc drive  
An apparatus and method are disclosed for recovering from a header error condition in a disc drive of the type having a rotatable disc having a plurality of concentric tracks with data fields for...
6205531 Method and apparatus for virtual address translation  
A method and apparatus for efficiently translating virtual to physical addresses is provided. An embodiment of the apparatus includes a TLB descriptor table that includes a series of TLB...