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6636925 Bus interface circuit preparation apparatus and recording medium  
An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a...
6629187 Cache memory controlled by system address properties  
A digital system is provided with a microprocessor (100), a cache (120) and various memory and devices (140a-140n). Signals to control certain cache memory modes are provided by a physical address...
6629189 Method and apparatus for managing target devices in a multi-path computer system  
A method and apparatus for managing at least one logical volume in a computer system that includes a processor, a storage system, and a plurality of paths coupling the processor to the storage...
6629199 DIGITAL DATA STORAGE SYSTEM INCLUDING DIRECTORY FOR EFFICIENTLY PROVIDING FORMATTING INFORMATION FOR STORED RECORDS AND UTILIZATION OF A CHECK VALUE FOR VERIFYING THAT A RECORD IS FROM A PARTICULAR STORAGE LOCATION  
A digital data storage system in the form of a mass storage subsystem in which information is stored on one or more disk storage units, with a storage element constituting a track on a disk...
6625712 Memory management table producing method and memory device  
The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information...
6625713 Memory controller and method for managing a logical/physical address control table  
A memory controller for reading data stored in a nonvolatile memory that includes a number of erasable blocks containing a number of pages. A logical/physical address control table stored in a...
6625708 Method and apparatus for dynamically defining line buffer configurations  
A method and apparatus of defining a line buffer configuration in a memory is disclosed. In one embodiment, the method and apparatus receives input data information and mode information, proceeds...
6622230 Multi-set block erase  
A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block...
6622231 Method and apparatus for paging data and attributes including an atomic attribute  
A digital data processing apparatus configured to selectively transfer data between a primary data storage element and an associated data file on a secondary data storage element. The apparatus...
6606698 Apparatus and method for managing data storage  
A data storage managing apparatus is described which translates a host Input/Output (I/O) request into a standard form. Thus, I/O requests sent by different hosts using different protocols are...
6604187 Providing global translations with address space numbers  
A processor provides a register for storing an address space number (ASN). Operating system software may assign different ASNs to different processes. The processor may include a TLB to cache...
6604184 Virtual memory mapping using region-based page tables  
The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual...
6604186 Method for dynamically adjusting memory system paging policy  
A method and apparatus of dynamically adjusting a memory system's existing paging policy is disclosed. In one embodiment, the method for dynamically adjusting the paging policy generates a select...
6593932 System for implementing a graphic address remapping table as a virtual register file in system memory  
A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references...
6594751 Method and apparatus for pointer relocation optimization for virtual memory mapping and transaction management in a database system  
There is provided an apparatus and a method for virtual memory mapping and transaction management for an object-oriented data base system having at least one permanent storage means for storing...
6591328 Non-volatile memory storing address control table data formed of logical addresses and physical addresses  
A non-volatile memory including a logical/physical address control table for controlling data recorded discretely in the non-volatile memory composed of a plurality of blocks each serving as a...
6587915 Flash memory having data blocks, spare blocks, a map block and a header block and a method for controlling the same  
A flash memory and a method for controlling the same are disclosed. The flash memory has units, each of which includes a plurality of data blocks for writing data; a plurality of spare blocks...
6581132 Flash memory system including a memory manager for managing data  
A flash memory system of the present invention comprises a memory manager for managing data transmission/reception between a host computer and a flash memory, said memory manager having an address...
6581130 Dynamic remapping of address registers for address translation between multiple busses  
Address translation between various peripheral bus interfaces is provided through a bus interface device. Specifically, the bus interface device translates incoming transactions from a source bus...
6578129 Optimized virtual memory management for dynamic data types  
The present invention proposes effective solutions for the design of Virtual Memory Management for applications with dynamic data types in an embedded (HW or SW) processor context. A structured...
6578128 Address management for a shared memory region on a multi-processor controller board  
A system having a memory with a plurality of contiguous processor memory regions and a plurality of processors. Each one of such processors is associated with a corresponding one of the processor...
6574721 Apparatus and method for providing simultaneous local and global addressing using software to distinguish between local and global addresses  
An apparatus and method provide simultaneous local and global addressing capabilities in a computer system. A global address space is defined that may be accessed by all processes. In addition,...
6571330 Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor  
A processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64...
6553478 Computer memory access  
A memory for a computer system that includes a plurality of memory banks which provide an interleaved memory region as well as X and Y memory regions. Each memory access address includes a most...
6553475 Memory system with address conversion based on inherent performance condition  
A memory system includes a memory including a plurality of memory regions operating based on an identical principle; and an address conversion device for converting a logical address into a...
6549901 Using transportable tablespaces for hosting data of multiple users  
Provided are mechanisms that may be used to support efficient exportation of user data stored in a database system. According to an aspect of the present invention, a database system is configured...
6549996 Scalable multiple address space server  
A method and apparatus are provided for managing the amount of memory available to processes within the computer system. Additional virtual address spaces are dynamically created to make more...
6542978 Externally identifiable descriptor for standard memory allocation interface  
The invention noninvasively provides information relating to memory space allocation. Memory space allocation information is maintained in a location that is known or identifiable outside of the...
6529996 Network attached virtual tape data storage subsystem  
The network attached virtual tape storage subsystem interconnects a plurality of tape devices with a plurality of data processors via a high bandwidth switching network to implement a virtual,...
6526473 Memory module system for controlling data input and output by connecting selected memory modules to a data line  
A memory module system for connecting only selected memory modules to a data line to control data input and output is disclosed. The memory module system has a multiplicity of memory modules for...
6526478 Raid LUN creation using proportional disk mapping  
A method and system for creating logical units (LUNs) in a RAID system by allocating proportional amounts of disk storage space to each LUN. Proportional allocation of disk space for different...
6523105 Recording medium control device and method  
An information recording/reproducing device includes a transfer control section for carrying out input/output of transfer data, a recording medium control section for carrying out writing...
6519690 Flexible address programming with wrap blocking  
A flexible address mapping method and mechanism allows mapping regions of a microcontroller's memory and I/O address spaces for a variety of applications by defining memory regions which are...
6516400 Data storage, data processing system and method  
When reading or writing data from or to a flash memory, a table indicating the correspondence between physical addresses of physical blocks composing together a storage area of the flash memory...
6513105 FIFO system with variable-width interface to host processor  
A computer system includes a RAM-based FIFO for buffering communications between a host processor and a remote serial-communications device. The FIFO provides for quadlet, doublet, and singlet...
6513101 Expiring host selected scratch logical volumes in an automated data storage library  
Disclosed are a data storage library and library computer processor implemented methods for expiring logical volumes in response to expiration selection from a host. A library server maintains a...
6510496 Shared memory multiprocessor system and method with address translation between partitions and resetting of nodes included in other partitions  
A symmetric multiprocessor (SMP) of hierarchical connection realizing an inter-partition shared memory has at the gateway of an inter-node connection switch from each node, a translator for...
6499091 System and method for synchronizing data mirrored by storage subsystems  
The present invention is directed to a system and method for synchronizing data between mirrored subsystems. A method for storing data may include receiving data suitable for storage to a first...
6496905 Write buffer with burst capability  
Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer...
6493816 Method and apparatus for encapsulating address translation for shared persistent virtual storage  
A preferred embodiment of the present invention provides an intelligent reference object (IRO), which is used to encapsulate address translation between shared address space (SAS) addresses and...
6487649 Microcomputer  
In a microcomputer intended for executing a multiplicity of user programs, a memory management unit ensures that none of the user programs can access other programs. However, in order to be able...
6484249 Apparatus and method for transferring data between address spaces with different segment lengths  
An apparatus and method for efficiently transferring a plurality of segmented data with various sizes. An address translation storage unit stores an address translation table which provides a...
6480943 Memory address interleaving and offset bits for cell interleaving of memory  
A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into...
6477616 Storage device, storage system, memory management method, recording medium, and computer data signal  
A CPU creates a file management BSI and a file management BPT in a zone 0 included in a flash memory storing directories and an FAT, and stores the created BSI and BPT in an SRAM. In response to a...
6473840 Data processing system having a network and method for managing memory by storing discardable pages in a local paging device  
A method in a data processing system for managing memory within the data processing system. A discardable page that is to be removed from the memory is identified. A determination is made as to...
6470436 Eliminating memory fragmentation and garbage collection from the process of managing dynamically allocated memory  
A hardware or software apparatus, or a combination of both, is used for efficiently managing the dynamic allocation, access and release of memory used in a computational environment. This...
6467014 Automatic mapping and efficient address translation for multi-surface, multi-zone storage devices  
Automated address mapping is achieved by a system and methodology which automatically reacts to changes in the disk configuration. Prior to utilizing the disk, disk configuration information is...
6463517 Apparatus and method for generating virtual addresses for different memory models  
An apparatus and method for generating virtual addresses for different types of memory models using an existing address generation unit. A processor can be configured to operate using either a...
6460126 Computer resource management system  
A system and method for managing scarce computer system memory resources has three aspects. A first aspect allows large data structures to be replaced by a pointer that causes an intentional fault...
6460071 System and method for managing client application state in a stateless web browser environment  
A system and method for maintaining application state information in a stateless environment. State data of arbitrary length is stored in a storage area at a location referenced by a storage...