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5394539 |
Method and apparatus for rapid data copying using reassigned backing pages
A data processing system, having virtual addressing capability, has a real storage manager to associate virtual storage locations with real storage by accessing page tables to determine the...
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5388242 |
Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on demand page swapping
A computer system employs multiple CPUs, all executing the same instruction stream, with multiple, identical memory modules storing duplicates of the same data and accessable by all the CPUs,...
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5386522 |
Dynamic physical address aliasing during program debugging
The physical memory of a computer may not be directly accessable to the operator during the operation of a program due to the operational requirements of the operating system. Direct access to the...
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5375214 |
Single translation mechanism for virtual storage dynamic address translation with non-uniform page sizes
A dynamic address translation mechanism uses a single translation look aside buffer (TLB) facility for pages of various sizes. The single TLB is supported by a small amount of special hardware....
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5319758 |
Method for managing multiple virtual storages divided into families
A multiple virtual storage management method which requests, by a first program allocated to a first virtual space, subordination of the first virtual space to a first one of the space families at...
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5282274 |
Translation of multiple virtual pages upon a TLB miss
Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and...
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5278963 |
Pretranslation of virtual addresses prior to page crossing
An address translation mechanism for generating real addresses, within a page. based on stride from a beginning translated address in the page. However, whenever there is a page crossing, an...
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5226132 |
Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system
Instead of translation from a space address to a segment table origin address (STO) by an ordinary instruction, translation to the STO is done by a space base register modify instruction which uses...
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5155852 |
Digital information coding system which evenly distributes valid input data to digital signal processors operating in parallel
A digital signal processing apparatus which is used for the computation of coding image signals or the like and a motion compensative operation method which uses a digital signal processing...
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5155826 |
Memory paging method and apparatus
A method and apparatus to operate a paged memory system which uses only a single, predetermined address per page as a memory-mapped address. When the single memory-mapped address is accessed...
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5129070 |
Method of using the memory in an information processing system of the virtual addressing type, and apparatus for performing the method
The method and apparatus for using the memory in an information processing system of the virtual addressing type is characterized in that a first memory domain DX is organized around a logical...
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5095420 |
Method and system for performing virtual address range mapping in a virtual storage data processing system
A linear data set is mapped to one or more non-main storage virtual data spaces. Portions of this data space are then selectively mapped to a "window" in an address space in which an application is...
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5058003 |
Virtual storage dynamic address translation mechanism for multiple-sized pages
A dynamic address translation mechanism includes a first directory-look-aside-table (DLAT) for 4KB page sizes and a second DLAT for 1MB page sizes. The page size does need not be known prior to...
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4992936 |
Address translation method and apparatus therefor
In a method and apparatus wherein a logical address of a main storage designated by a program is translated into a real address: an address translation table for each of a plurality of address...
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4991082 |
Virtual storage system and method permitting setting of the boundary between a common area and a private area at a page boundary
An area boundary between a system common area and a job private area is set at any page boundary independently from a segment boundary, and for the segment (boundary segment) containing the area...
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4985828 |
Method and apparatus for generating a real address multiple virtual address spaces of a storage
A multiple virtual space control in a multiple virtual storage system having an address translation table used to translate a logical address to a real address, a control register for holding a...
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4961134 |
Method for minimizing locking and reading in a segmented storage space
A page-accessing method in a segmented tablespace 10 which eliminates unnecessary reading and locking. The tablespace comprises data pages 18 grouped into identically-sized segments 16, each...
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4835734 |
Address translation apparatus
A virtual space is divided into a plurality of areas of different memory block size, and a plurality of address translation modes are executed using different memory block sizes and based upon a...
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4812969 |
Address translation unit
An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative...
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4761737 |
Method to automatically increase the segment size of unix files in a page segmented virtual memory data processing system
A memory management system method increases the size of a segment in blocks of 64K virtual pages in response to the system detecting that the requested page has been protected. The conventional...
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4691281 |
Data processing system simultaneously carrying out address translation of a plurality of logical addresses
In a data processing system for use in carrying out address translation of a preselected logical address so as to access a sequence of data elements stored in a memory (32) with an interval left...
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4521846 |
Mechanism for accessing multiple virtual address spaces
The disclosure provides a general purpose register (GR) mask which associates predesignated address spaces with respective GRs assigned to contain a base value for calculating logical addresses...
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4500961 |
Page mode memory system
A multi-page ROM uses programmable pointers for selection of a page. The pointers each have a preliminary latch circuit, an output latch circuit, and a delay circuit. The preliminary latch circuit...
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4495565 |
Computer memory address matcher and process
An address matcher and process for same used as an aid in debugging computer programs. Each of a plurality of random access memories (RAMs) is addressed by a different subfield of a computer memory...
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4368513 |
Partial roll mode transfer for cyclic bulk memory
Latency of a cyclic bulk storage device attached to a CPU and a main storage through standard channel facilities is reduced without modification of the channel and CPU hardwares. The storage device...
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4355355 |
Address generating mechanism for multiple virtual spaces
The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The...
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4326248 |
Multiple virtual storage control system
A multiple virtual storage control system for a data processing system for handling a plurality of virtual spaces is disclosed. Virtual addresses indicative of addresses in the virtual spaces are...
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4277826 |
Synchronizing mechanism for page replacement control
An apparatus provides synchronization for page replacement control in a paged, virtual memory environment in which either the CPU or the I/O devices may pin and unpin pages to control their...
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4158227 |
Paged memory mapping with elimination of recurrent decoding
A memory expansion apparatus is disclosed which provides for expansion of memory capacity by use of logic associated with memory modules. The logic provides for selection of one of a plurality of...
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4145738 |
Plural virtual address space processing system
In a data processing system having a plurality of virtual address spaces, a virtual address is translated into a real address for accessing a main memory and the translation result is stored in a...
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4079453 |
Method and apparatus to test address formulation in an advanced computer system
In a large scale data processing system employing partitioning, paging and segmentation techniques with a descriptor enforced access to storage areas, a method and apparatus for testing address...
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4056848 |
Memory utilization system
An apparatus is provided which allows computer programs to execute directly out of a large, sector addressable secondary memory by utilizing a relatively small, word addressable buffer memory. The...
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4044334 |
Database instruction unload
One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented...
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3990051 |
Memory steering in a data processing system
In an input/output data processing system employing local and remote memory and paged data storage, memory steering is included in the address development, thus eliminating the need for special...
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3938096 |
Apparatus for developing an address of a segment within main memory and an absolute address of an operand within the segment
Computer addressing hardware and a method of address development which utilizes the concept of a segment as the unit of addressability is disclosed. The fundamental vehicle for addressing is the...
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3813652 |
MEMORY ADDRESS TRANSFORMATION SYSTEM
A system is disclosed in which an input binary address is transformed into a set of module select signals and a set of address signals whereby an aggregate of memory modules, each of which may...
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