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9015400 Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk (HWTW)  
A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation...
9015437 Extensible hardware device configuration using memory  
The present disclosure provides a system and method for implementing extensible hardware configuration using memory. A memory containing an Info Block is provided. The Info Block contains a set of...
9009386 Systems and methods for managing read-only memory  
A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further...
9003161 Systems and methods for managing read-only memory  
A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized...
8990422 TCP segmentation offload (TSO) using a hybrid approach of manipulating memory pointers and actual packet data  
Systems, apparatusses, and methods are disclosed for transmission control protocol (TCP) segmentation offload (TSO). A hardware TSO engine is capable of handling segmentation of data packets and...
8972648 Kernal memory locking for systems that allow over-commitment memory  
Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical...
8972647 Kernel memory locking for systems that allow over-commitment memory  
Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical...
8954710 Variable length encoding in a storage system  
A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries...
8954697 Access to shared memory segments by multiple application processes  
A system configures page tables to cause an operating system to copy original page data in a data store when any one of the application processes makes a first write request for the original page...
8949571 Synchronizing a translation lookaside buffer with an extended paging table  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
8938572 Virtual machine memory page sharing system  
Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how...
8898423 High performance caching architecture for data storage systems  
A data storage system is disclosed that utilizes a high performance caching architecture. In one embodiment, the caching architecture utilizes a cache table, such as a lookup table, for...
8856489 Logical sector mapping in a flash storage array  
A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem...
8843727 Performance enhancement of address translation using translation tables covering large address spaces  
An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset...
8832351 Virtualizing processor memory protection with “L1 iterate and L2 drop/repopulate”  
In a computing system including a processor and virtualization software including a guest operating system (OS) that utilizes a guest domain access control register (DACR) containing domain access...
8819393 Facilitating management of storage of a pageable mode virtual environment absent intervention of a host of the environment  
Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent...
8806175 Hybrid hash tables  
A hash table system having a first hash table and a second hash table is provided. The first hash table may be in-memory and the second hash table may be on-disk. Inserting an entry to the hash...
8799622 Method for managing a memory apparatus  
A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid...
8793428 System and method to reduce trace faults in software MMU virtualization  
A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained...
8782338 Method for wear leveling in a nonvolatile memory  
A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data,...
8719543 Systems and methods implementing non-shared page tables for sharing memory resources managed by a main operating system with accelerator devices  
Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of...
8706947 Virtual machine memory page sharing system  
Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how...
8688952 Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB  
An arithmetic processing apparatus includes: a plurality of TLBs holding as entries a portion of a conversion table for conversion of virtual addresses into physical addresses that has been placed...
8683174 I/O conversion method and apparatus for storage system  
A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A...
8645664 Logical sector mapping in a flash storage array  
A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem...
8627041 Efficient line and page organization for compression status bit caching  
One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of...
8612721 Semiconductor memory controlling device  
According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has...
8607026 Translation lookaside buffer  
A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory...
8601233 Synchronizing a translation lookaside buffer with an extended paging table  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
8601223 Techniques for servicing fetch requests utilizing coalesing page table entries  
A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of...
8595465 Virtual address to physical address translation using prediction logic  
Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors...
8578088 Method for wear leveling in a nonvolatile memory  
A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data,...
8499117 Method for writing and reading data in a nonvolatile memory, by means of metadata  
A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a...
8495318 Memory page management in a tiered memory system  
Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each...
8429378 System and method to manage a translation lookaside buffer  
A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory...
8417872 Write and merge methods in memory card systems for reducing the number of page copies  
A memory card system and related write method are disclosed. The method includes receiving a write request for a predetermined page; performing a write operation on a first log block that...
8397051 Hybrid hash tables  
A hash table system having a first hash table and a second hash table is provided. The first hash table may be in-memory and the second hash table may be on-disk. Inserting an entry to the hash...
8375195 Accessing memory locations for paged memory objects in an object-addressed memory system  
One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the...
8364910 Hard object: hardware protection for software objects  
In accordance with one embodiment, additions to the standard computer microprocessor architecture hardware are disclosed comprising novel page table entry fields 015 062, special registers 021...
8296546 Synchronizing a translation lookaside buffer with an extended paging table  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
8281105 I/O conversion method and apparatus for storage system  
A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A...
8274508 Method for representing objects with concentric ring signature descriptors for detecting 3D objects in range images  
A 3D object is represented by a descriptor, wherein a model of the 3D object is a 3D point cloud. A local support for each point p in the 3D point cloud is located, and reference x, y, and z axes...
8261003 Apparatus and methods for managing expanded capacity of virtual volumes in a storage system  
Methods and apparatus for expanded capacity virtual volumes in a virtualized storage system. A storage controller of the storage system parses a SCSI command block as it is received to generate a...
8239619 Method and apparatus for high-speed byte-access in block-based flash memory  
Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored...
8219781 Method for managing a memory apparatus, and associated memory apparatus thereof  
A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block during accessing pages of the block;...
8219776 Logical-to-physical address translation for solid state disks  
Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a...
8219780 Mitigating context switch cache miss penalty  
Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a...
8214622 Facilitating management of storage of a pageable mode virtual environment absent intervention of a host of the environment  
Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent...
8190853 Calculator and TLB control method  
A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro...
8176239 Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card  
A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following...

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