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9043612 Protecting visible data during computerized process usage  
Embodiments of the present invention provide an approach for protecting visible data during computerized process usage. Specifically, in a typical embodiment, when a computerized process is...
9032398 Online classification of memory pages based on activity level represented by one or more bits  
Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The...
9015400 Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk (HWTW)  
A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation...
9015447 Memory system comprising translation lookaside buffer and translation information buffer and related method of operation  
A memory system comprises a translation lookaside buffer (TLB) configured to receive a virtual address and to search for a TLB entry matching the virtual address, and a translation information...
9015027 Fast emulation of virtually addressed control flow  
Two or more processes for executing a source application are emulated using: a virtual trampoline memory in which each emulated process has a respective private trampoline memory; and a shared...
9009442 Data writing method, memory controller and memory storage apparatus  
A data writing method and a memory controller and a memory storage apparatus using the same are provided. The method includes selecting physical units as a global random area and building a global...
9009446 Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with electrical interconnect  
The disclosed embodiments provide a system that uses broadcast-based TLB-sharing techniques to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes...
9009445 Memory management unit speculative hardware table walk scheme  
A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available...
9003164 Providing hardware support for shared virtual memory between local and remote physical memory  
In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location...
9003163 Combining a remote TLB lookup and a subsequent cache miss into a single coherence operation  
The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For...
8990542 Efficient metadata protection system for data storage  
A method for protecting page-level metadata in a storage system is provided. The method includes providing in a page table first protection data, receiving a command to read data from a page of...
8988107 Integrated circuit including pulse control logic having shared gating control  
An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal....
8984255 Processing device with address translation probing and methods  
A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of...
8984254 Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance  
A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in...
8966221 Translating translation requests having associated priorities  
A lookup operation is performed in a translation look aside buffer based on a first translation request as current translation request, wherein a respective absolute address is returned to a...
8966200 Pruning free blocks out of a decremental backup chain  
Pruning free blocks out of a decremental backup chain. In one example embodiment, a method for pruning free blocks out of a decremental backup in a decremental backup chain includes identifying a...
8959302 Computer system, server module, and storage module  
An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a...
8959303 Information processor and multi-core system  
According to one embodiment, an information processor includes an operator and an address protector. The address protector includes a register access interface, an address table, and an access...
8954709 Memory management apparatus, memory management method and non-transitory computer readable storage medium  
A memory management apparatus has an ASID conversion table, an actual ASID use table, and a TLB flush control section. The ASID conversion table and the actual ASID use table manage virtual ASID,...
8954648 Memory device and operating method thereof  
The invention provides a memory device. In one embodiment, the memory device comprises a flash memory, a memory, and a controller. The flash memory comprises a plurality of blocks for data...
8954697 Access to shared memory segments by multiple application processes  
A system configures page tables to cause an operating system to copy original page data in a data store when any one of the application processes makes a first write request for the original page...
8949573 Translation lookaside buffer structure including an output comparator  
A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated...
8949571 Synchronizing a translation lookaside buffer with an extended paging table  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
8949572 Effective address cache memory, processor and effective address caching method  
An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a...
8943297 Parallel read functional unit for microprocessors  
A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and...
8938602 Multiple sets of attribute fields within a single page table entry  
A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The...
8938571 Managing I/O operations in a virtualized environment  
A set of techniques is described for performing input/output (I/O) between a guest domain and a host domain in a virtualized environment. A pool of memory buffers is reserved for performing...
8938575 Minimized half-select current in multi-state memories  
A multi-state memory system with encoding that minimizes half-select currents. The system includes an array of row and column conductors with a plurality of storage cells each capable of being...
8930674 Systems and methods for accessing a unified translation lookaside buffer  
Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss...
8924684 Virtual memory management to reduce address cache flushing during I/O operations  
Approaches are described for reducing the number of memory address cache (e.g. TLB) flushes that need to be performed during the course of performing virtualized I/O. A device driver residing in a...
8924648 Method and system for caching attribute data for matching attributes with physical addresses  
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
8924685 Configuring surrogate memory accessing agents using non-priviledged processes  
Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first...
8914611 Address translation device, processing device and control method of processing device  
An address translation buffer (TLB) which holds pairs of virtual addresses and physical addresses by respective page sizes and performs an address translation, a storage unit which holds a pair of...
8914609 Modifying data storage in response to detection of a memory system imbalance  
A computing device includes an interface, memory, and a processing module. The memory stores a directory and inode tables. The directory stores a file identifier and a corresponding inumber for...
8909870 Cache evictions from data cache based on content of address translation table cache and address translation table  
A storage device includes a non-volatile memory, a cache memory and a memory controller. The non-volatile memory stores a logical-to-physical address translation table for managing partitioned...
8909851 Storage control system with change logging mechanism and method of operation thereof  
A method of operation of a storage control system including: providing a memory controller; accessing a volatile memory table by the memory controller; writing a non-volatile semiconductor memory...
8904123 Transferring learning metadata between storage servers having clusters via copy services operations on a shared virtual logical unit that stores the learning metadata  
A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device...
8898371 Accessing logical-to-physical address translation data for solid state disks  
Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device,...
8898430 Fault handling in address translation transactions  
A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address...
8898429 Application processor and a computing system having the same  
An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes one page table. The peripheral...
8892846 Metadata management for virtual volumes  
Methods, apparatus, and systems, including computer programs encoded on a computer storage medium, manage metadata for virtual volumes. In some implementations, a method includes: loading into...
8880844 Inter-core cooperative TLB prefetchers  
A chip multiprocessor includes a plurality of cores each having a translation lookaside buffer (TLB) and a prefetch buffer (PB). Each core is configured to determine a TLB miss on the core's TLB...
8874869 Semiconductor memory device  
In a semiconductor memory device, an update data control circuit is provided, which selectively couples a physical address input data line or an effective address input data line to a common input...
8868863 Method and apparatus for a frugal cloud file system  
Various embodiments provide a method and apparatus of providing a frugal cloud file system that efficiently uses the blocks of different types of storage devices with different properties for...
8868865 Computer system, server module, and storage module  
An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a...
8868822 Data-processing method, program, and system  
A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and...
8868847 Multi-core processor snoop filtering  
Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit...
8862859 Efficient support of multiple page size segments  
An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported...
8856425 Method for performing meta block management, and associated memory device and controller thereof  
A method for performing meta block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks...
8856490 Optimizing TLB entries for mixed page size storage in contiguous memory  
A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises...