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6175906 Mechanism for fast revalidation of virtual tags  
A recovery mechanism to eliminate the need to re-fetch cache entries during virtual-to-physical memory re-mapping by reducing accesses and thus the demand on the table lookaside buffer (TLB) during...
6161166 Instruction cache for multithreaded processor  
A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory...
6157986 Fast linear tag validation unit for use in microprocessor  
A linearly addressed cache capable of fast linear tag validation after a context switch or a translation lookaside buffer (TLB) flush. The cache is configured to validate multiple linear address...
6138188 Buffer management device and method for improving buffer usage and access performance in data processing system  
A buffer management device and method for improving buffer usage and access performance in a data processing system. A buffer device is located between two components in the data processing system...
6138203 Information processing apparatus and method enabling a write-once recording medium to be utilized as a rewriteable recording medium  
An information processing apparatus and information processing method enables a write once type disc to be used as a rewritable recording medium. There can be realized an address control mechanism...
6138226 Logical cache memory storing logical and physical address information for resolving synonym problems  
Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area...
6138223 Absolute address history table index generation for predicting instruction and operand cache accesses  
A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which...
6138225 Address translation system having first and second translation look aside buffers  
A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a...
6128684 Bus bridge  
Disclosed is a bus bridge for mutually connecting a memory bus having memories connected thereto and an I/O bus having plural I/O devices connected thereto, which comprises a conversion table in...
6128664 Address-translating connection device  
An address-translating connection device which makes it possible to dynamically assign an IP address to a private address when a connection is made to inside of a LAN from outside. When an inquiry...
6125433 Method of accomplishing a least-recently-used replacement scheme using ripple counters  
An optimized translation lookaside buffer (TLB) utilizes a least-recently-used algorithm for determining the replacement of virtual-to-physical memory translation entries. The TLB is faster and...
6119204 Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization  
A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor...
6105110 Circuit and method for replacement of address translations  
A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical...
6092172 Data processor and data processing system having two translation lookaside buffers  
A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address...
6078987 Translation look aside buffer having separate RAM arrays which are accessable with separate enable signals  
A unified array access for two logically different arrays is provided. The first array includes CAM cells arranged in n rows and x columns. At least one CAM cell is coupled to a match line, a CAM...
6079004 Method of indexing a TLB using a routing code in a virtual address  
The method serves to operate an address translation device for translating a virtual address of a virtual address space comprising a plurality of pages into a physical address of a physical address...
6073224 Network interface circuit with replacement circuitry and method for segregating memory in an address translation unit with locked and unlocked regions  
A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a portion of the memory that can be...
6065091 Translation look-aside buffer slice circuit and method of operation  
For use in an x-86 processor having a physically-addressable cache and an associated translation look-aside buffer (primary TLB) that stores corresponding logical and physical addresses for...
6049857 Apparatus and method for translating addresses utilizing an ATU implemented within a network interface card  
An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address...
6047365 Multiple entry wavetable address cache to reduce accesses over a PCI bus  
A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address...
6044447 Method and apparatus for communicating translation command information in a multithreaded environment  
A method and apparatus are provided for communicating translation command information in a multithreaded environment in a computer system. The computer system includes a processor unit, an...
6044446 Mechanism to reduce interprocessor traffic in a shared memory multi-processor computer system  
A system for reducing query traffic in multi-processor shared memory system utilizes the inclusion of an unshared bit in translation table entries in the address translation system. A query system...
6038639 Data file storage management system for snapshot copy operations  
The present data file storage management system for snapshot copy operations maintains a two level mapping table which enables the data files to be copied using the snapshot copy process and only...
6035393 Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution  
A computer system includes an instruction prefetching mechanism that detects whether an instruction to be prefetched is located in a region of memory that is uncacheable. To perform an instruction...
6032241 Fast RAM for use in an address translation circuit and method of operation  
There is disclosed, for use in an x86-compatible processor having a physically-addressable cache, an address translation device for translating linear addresses received from a plurality of linear...
6026476 Fast fully associative translation lookaside buffer  
A fast, fully associative translation lookaside buffer (TLB) with the ability to store and manage information pertaining to at least two different page sizes is disclosed. The TLB utilizes a tag...
6026467 Content-addressable memory implemented with a memory management unit  
A content-addressable memory (CAM) is implemented by using otherwise-unused memory management unit (MMU 102) and cache memories (104, 105) of a program-controlled microprocessor (100). A program...
6023704 Apparatus and method for swapping identities of two objects to reference the object information of the other  
An object identity swapper dynamically updates the configuration of an object by taking a first object, instantiating a new second object, swapping the identities of the first and second objects,...
6021481 Effective-to-real address cache managing apparatus and method  
An effective-to-real address translation cache management apparatus and method utilizes an effective-to-real address translation cache segment register latch having a bit corresponding to each of...
6012132 Method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table  
A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an...
6012133 Mutually controlled match-line-to-word-line transfer circuit  
A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic...
6012134 High-performance processor with streaming buffer that facilitates prefetching of instructions  
A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers...
6012131 High speed translation lookaside buffer employing content address memory  
A translation lookaside buffer (TLB) for use of a microprocessor, using a content address memory (CAM), includes a block for generating a control clock for precharging a clock and an enable clock...
6012135 Computer having multiple address ports, each having logical address translation with base and limit memory management  
Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port...
6006312 Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses  
A separate cacheable-in-virtual-cache attribute bit (CV) is maintained for each page of memory in the translation table maintained by the operating system. The CV bit indicates whether the memory...
6003123 Memory system with global address translation  
A multiprocessor system having shared memory uses guarded pointers to identify protected segments of memory and permitted access to a location specified by the guarded pointer. Modification of...
6000021 Apparatus and method for extending the useful life of a data storage system  
Useful life extension for a data storage system in which either or both of read/write probes and storage areas are components subject to wear caused by the access operations. An access counter...
5999933 Process and apparatus for collecting a data structure of a memory dump into a logical table  
A hardware/software system for analyzing memory dumps. The system collects data structures in a memory dump into logical tables, one logical table per selected type of data structure. The logical...
6000008 Method and apparatus for matching data items of variable length in a content addressable memory  
A content addressable memory (CAM) structure, and a method for its use, wherein data items of different selected lengths stored in the CAM may be located by matching sequences of CAM data words...
5996054 Efficient virtualized mapping space for log device data storage system  
A log device based data storage subsystem provides for the efficient storage and retrieval of data with respect to an operating system executing on a computer system coupled to the data storage...
5995420 Integrated XNOR flip-flop for cache tag comparison  
An integrated XNOR flip-flop is provided which is faster than conventional XNOR flip-flop combinations. The integrated XNOR flip-flop is faster and uses less area than conventional XNOR flip-flop...
5991854 Circuit and method for address translation, using update and flush control circuits  
A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical...
5991848 Computing system accessible to a split line on border of two pages within one cycle  
This invention is developed to provide a computing system which can carry out a high speed access to a cache memory within one cycle even though data needed to be read is on the border of two...
5987584 Wavetable address cache to reduce accesses over a PCI bus  
A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address...
5983332 Asynchronous transfer mode (ATM) segmentation and reassembly unit virtual address translation unit architecture  
An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address...
5970512 Translation shadow array adder-decoder circuit for selecting consecutive TLB entries  
A combined adder/decoder calculates a field within an effective address necessary to access a translation array. Rather than adding the full lengths of the previous fetch address and offset, only...
5966736 Multiplexing DRAM control signals and chip select on a processor  
A DRAM controller is incorporated onto an existing microcontroller architecture. Existing chip select signals or other signals on the microcontroller are multiplexed with RAS and CAS signals. The...
5963984 Address translation unit employing programmable page size  
Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside...
5956752 Method and apparatus for accessing a cache using index prediction  
Index prediction is used to access data in a memory array. A virtual address is received at an input. The virtual address is translated to a physical address. The memory array is accessed at a...
5956756 Virtual address to physical address translation of pages with unknown and variable sizes  
A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be...
Matches 401 - 450 out of 740 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >