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6385712 |
Method and apparatus for segregation of virtual address space
A method and apparatus for segregation of virtual address space in a computer system is provided. An embodiment of the invention provides compatibility of an emulated processor architecture with a...
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6374341 |
Apparatus and a method for variable size pages using fixed size translation lookaside buffer entries
The present invention provides an apparatus and a method for variable size pages using fixed size TLB (Translation Lookaside Buffer) entries. In one embodiment, an apparatus for variable size pages...
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6374342 |
Translation lookaside buffer match detection using carry of lower side bit string of address addition
There is disclosed DTLB in a microprocessor of the present invention, comprising an adder for adding a base address and a sign-extended offset address; a comparator for judging whether or not upper...
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6351796 |
Methods and apparatus for increasing the efficiency of a higher level cache by selectively performing writes to the higher level cache
Methods and apparatus for storing data in a multi-level memory hierarchy having at least a lower level cache and a higher level cache. Relevancy information is maintained for various data values...
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6351797 |
Translation look-aside buffer for storing region configuration bits and method of operation
There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address...
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6349372 |
Virtual uncompressed cache for compressed main memory
System and method for reducing data access latency for cache miss operations in a computer system implementing main memory compression in which the unit of compression is a memory segment. The...
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6349362 |
Scheme to partition a large lookaside buffer into an L2 cache array
A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the...
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6349380 |
Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or...
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6339816 |
Method for improving controllability in data processing system with address translation
When there are write accesses to user pages in a data processing system that are marked as write-protected in a translation memory, the method checks, after an interrupt request, a corresponding...
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6332184 |
Method and apparatus for modifying memory accesses utilizing TLB entries
A method and apparatus includes processing for modifying memory accesses, which begins by receiving a memory transaction. The processing continues by determining whether a translation look-aside...
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6329985 |
Method and apparatus for graphically displaying mapping of a logical object
A method and apparatus for manipulating data in a storage device that is coupled to a host computer. Manipulations that can be performed by the storage device include moving non-contiguous blocks...
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6327646 |
Translation look-aside buffer utilizing high-order bits for fast access
A fast translation look-aside buffer for translating a linear address R L =A+B to a physical address, where A and B are two N bit operands. Inputs to the translation look-aside buffer are the n...
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6324635 |
Method and apparatus for address paging emulation
A method and apparatus for address paging emulation includes processing that begins by producing an extended logical address in response to a memory access request. The extended logical address...
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6324634 |
Methods for operating logical cache memory storing logical and physical address information
Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area...
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6304944 |
Mechanism for storing system level attributes in a translation lookaside buffer
A method and apparatus for improving the efficiency of the cacheability (and other attribute) determination by making the information from the region register available during linear to physical...
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6304951 |
Data processing system and method for generating virtual memory descriptors including pretranslated physical addresses
A data processing system and method are described for generating virtual memory descriptors which include pretranslated physical addresses. The data processing system has a virtual memory address...
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6304962 |
Method and apparatus for prefetching superblocks in a computer processing system
A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch...
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6301647 |
Real mode translation look-aside buffer and method of operation
There is disclosed, for use in an x86-compatible processor capable of operating in real mode and paging mode and having a physically-addressable cache, an address translation device for providing...
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6301648 |
Method and apparatus for processing memory accesses utilizing a TLB
A method and apparatus for processing memory access requests having enhanced functionality includes processing that begins by receiving a memory access request. The process continues by determining...
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6298411 |
Method and apparatus to share instruction images in a virtual cache
A method of accessing information in a cache of a multithreaded system comprises providing a virtual address of an instruction to be accessed by a thread. Upon a cache miss, the physical address of...
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6289431 |
Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries
A method and apparatus for accessing pages in physical memory, where the physical memory is described. The present invention provides a paged memory system having multiple page sizes. Pages of a...
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6286090 |
Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches
A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table...
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6286092 |
Paged based memory address translation table update method and apparatus
A page based memory address translation table update method and apparatus uses a first processor, such as a host processor or other processor, to notify a second processor to update its own page...
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6286091 |
Microprocessor using TLB with tag indexes to access tag RAMs
A microprocessor is disclosed, which determines hit/miss by comparing four tag RAMs 5×4 times to improve economical efficiency of a device. The microprocessor includes a first latch for reserving...
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6279097 |
Method and apparatus for adaptive address lookup table generator for networking application
A method of generating a lookup table includes receiving an input address; generating a compressed address from the input address, the compressed address having fewer bits than the input address;...
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6275917 |
High-speed address translation system
In a high-speed address translation system provided in a computer system including a logical address space storing logical addresses, a physical address space for storing physical addresses and a...
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6272597 |
Dual-ported, pipelined, two level cache system
A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency...
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RE37305 |
Virtual memory address translation mechanism with controlled data persistence
A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly...
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6266755 |
Translation lookaside buffer with virtual address conflict prevention
A translation lookaside buffer for detecting and preventing conflicting virtual addresses from being stored therein is disclosed. Each entry in the buffer is associated with a switch which can be...
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6266752 |
Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed...
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6263403 |
Method and apparatus for linking translation lookaside buffer purge operations to cache coherency transactions
A method and apparatus link translation lookaside buffer (TLB) purge operations to cache coherency transactions, thereby allowing the TLB purge operations to be performed by hardware without...
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6240509 |
Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation
In one embodiment of the invention, a processor includes an execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also...
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6240501 |
Cache-less address translation
A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to the local memory space of a node...
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6240484 |
Linearly addressable microprocessor cache
A microprocessor conforming to the X86 architecture is disclosed which includes a linearly addressable cache, thus allowing the cache to be quickly accessed by an external bus while allowing fast...
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6237073 |
Method for providing virtual memory to physical memory page mapping in a computer operating system that randomly samples state information
A method is provided for guiding virtual-to-physical mapping policies in a computer system including a processor and a memory. State information is randomly sampled from selected memory references...
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6233666 |
Deferred disk drive space allocation for virtual memory pages with management of disk address recording in multipage tables without external process interrupts for table for input/output to memory
A data processor controlled system for providing virtual memory comprising a data processor memory for storing a plurality of real memory pages, secondary storage unit and a memory management...
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6226732 |
Memory system architecture
A memory architecture includes a virtual memory system and a physical memory system. For one mode of operation all memory accesses are performed within the virtual memory system. For a second mode...
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6226733 |
Address translation mechanism and method in a computer system
An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed...
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6223263 |
Method and apparatus for locking and unlocking a memory region
A method and apparatus for managing a memory region that stores locked and unlocked data. Data stored in the memory region is accessed. The data has an associated index that is stored in a locked...
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6219758 |
False exception for cancelled delayed requests
A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses...
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6212613 |
Methods and apparatus for reusing addresses in a computer
A technique reuses addresses in a computer that includes a memory and a translation lookaside buffer having entries for storing address mappings for address translation. The technique involves...
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6209057 |
Storage device having data buffer
In a storage device in which data is read ahead and stored in a cache memory during reading of data from a medium, a data buffer is managed so that the probability that data to be read is found in...
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6205531 |
Method and apparatus for virtual address translation
A method and apparatus for efficiently translating virtual to physical addresses is provided. An embodiment of the apparatus includes a TLB descriptor table that includes a series of TLB...
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6202127 |
Apparatus for spatial and temporal sampling in a computer memory system
An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a...
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6199147 |
Distributed-memory multiprocessor computer system with directory-based cache coherency with ambiguous mappings of cached data to main-memory locations
A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient...
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6199152 |
Translated memory protection apparatus for an advanced microprocessor
A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps...
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6192487 |
Method and system for remapping physical memory
A method and system for remapping physical memory that is malfunctioning. The physical memory has memory locations with addresses. The addresses are ordered from a lowest to a highest address, and...
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6192371 |
Object morphing in an object oriented computing environment using relational database query procedure
A method, system and computer program product are disclosed for morphing an object from one class to another in an object oriented computing environment implemented by a relational database. Object...
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6189078 |
System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency
A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a...
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6175898 |
Method for prefetching data using a micro-TLB
A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching...
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