|
Match
|
Document |
Document Title |
|
|
6622229 |
Virtual memory structure
An exemplary embodiment of the invention is a virtual memory structure having a first virtual memory space and a virtual page frame table space. The first virtual memory space includes at least one...
|
|
|
6615337 |
Method and apparatus for maintaining coherency in a translation lookaside buffer
In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit...
|
|
|
6606697 |
Information processing apparatus and memory control method
A page table on a main storage contains a correspondence between guest virtual address and a host real address, and a TLB in a processor holds said correspondence calculated by a previous address...
|
|
|
6604184 |
Virtual memory mapping using region-based page tables
The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual...
|
|
|
6604185 |
Distribution of address-translation-purge requests to multiple processors
A method and apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing...
|
|
|
6598147 |
Data processing device and method
The present invention has for its object to provide a data processing apparatus which improves the point that in data processing employing an associative storage device, performing the high speed...
|
|
|
6594734 |
Method and apparatus for self modifying code detection using a translation lookaside buffer
Self modifying code is detected using a translation lookaside buffer in order to provide cache coherency. The translation lookaside buffer has physical page addresses stored therein over which...
|
|
|
6593931 |
Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles
An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first...
|
|
|
6594750 |
Method and apparatus for handling an accessed bit in a page table entry
A method and apparatus for handling an accessed bit in a page table entry is provided. When a page table entry is not present in a translation lookaside buffer (TLB), an electrical circuit causes a...
|
|
|
6594704 |
Method of managing and using multiple virtual private networks in a router with a single routing table
A method of maintaining multiple routing tables within a global table of a network router including the steps of providing the router with a route table generator to maintain the global table, and...
|
|
|
6591343 |
Predecode in parallel with TLB compare
An apparatus and method are provided for determining initial information about a macro instruction prior to decoding of the macro instruction by translation logic within a pipeline microprocessor....
|
|
|
6591340 |
Microprocessor having improved memory management unit and cache memory
Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is...
|
|
|
6587933 |
Method, system, and program for discarding data in a storage system where updates to a primary storage device are shadowed in a secondary storage device
Provided is a method, system, and program for releasing storage space in a first and second storage devices. Updates to the first storage device are copied to the second storage device to provide...
|
|
|
6564311 |
Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit
An address translation apparatus comprises: entry storage means for storing a plurality of entries, each entry containing a virtual page number, a physical page number, and a process identifier...
|
|
|
6560687 |
Method of implementing a translation lookaside buffer with support for a real space control
To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the...
|
|
|
6560675 |
Method for controlling concurrent cache replace and return across an asynchronous interface
The present invention provides a method and a computer system that compares a portion of a signal and information transferred from a cache memory, while the information is in transit from the cache...
|
|
|
6553477 |
Microprocessor and address translation method for microprocessor
A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The...
|
|
|
6549997 |
Dynamic variable page size translation of addresses
The current disclosure concerns dynamic variable page size translation of addresses. Such translation can be achieved at higher clock speeds than have heretofore been possible due to the use of a...
|
|
|
6539466 |
System and method for TLB buddy entry self-timing
A self-timed translation lookaside buffer (TLB) is disclosed that utilizes a two-level match scheme to trigger the evaluation of whether a match is achieved for a received virtual address within...
|
|
|
6535970 |
Method and apparatus for enhanced performance caching for path names
A method and apparatus are provided for enhanced performance caching for path names. A vnode is built for a root directory and a path name is stored in a path cache for the vnode for the root...
|
|
|
6532528 |
Data processor and data processor system having multiple modes of address indexing and operation
A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address...
|
|
|
6529998 |
Adaptive prefetching of data from a disk
A method for adaptively selecting an optimal pre-fetch policy between a first pre-fetch policy, in which a request for desired data from a data-set is satisfied by reading the desired data, and a...
|
|
|
6526497 |
Memory cache with sequential page indicators
A memory for storing address translation data includes one or more page table entry structures. Each page table entry structure includes a base address field to identify an allocated page of...
|
|
|
6523096 |
Apparatus for and method of accessing a storage region across a network
N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon...
|
|
|
6523104 |
Mechanism for programmable modification of memory mapping granularity
An apparatus and method are provided that enable system designers to have programmable minimum memory page sizes. The apparatus has a memory management unit (MMU) for storing a plurality of page...
|
|
|
6510507 |
Page address look-up range ram
A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address 410 (often representing a...
|
|
|
6510508 |
Translation lookaside buffer flush filter
A translation lookaside buffer (TLB) flush filter. In one embodiment, a central processing unit includes a TLB for storing recent address translations. A TLB flush filter monitors blocks of memory...
|
|
|
6496909 |
Method for managing concurrent access to virtual memory data structures
In a method for providing concurrent access to virtual memory data structures, a lock bit for locking a virtual page data structure is provided in a page table entry of a page table. The page table...
|
|
|
6493816 |
Method and apparatus for encapsulating address translation for shared persistent virtual storage
A preferred embodiment of the present invention provides an intelligent reference object (IRO), which is used to encapsulate address translation between shared address space (SAS) addresses and...
|
|
|
6493812 |
Apparatus and method for virtual address aliasing and multiple page size support in a computer system having a prevalidated cache
A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support for various levels of address...
|
|
|
6490671 |
System for efficiently maintaining translation lockaside buffer consistency in a multi-threaded, multi-processor virtual memory system
A method for maintaining virtual memory consistency in a multi-processor environment comprises allocating a subset of virtual memory to a process, and mapping the subset of virtual memory to a...
|
|
|
6480950 |
Software paging system
A method for translating, in a software paging system, an input key describing a virtual page to the address of the page in main memory, comprises creating, in main memory, a translation buffer...
|
|
|
6477634 |
Physical pages de-allocation method for virtual addressing machine
In a computer system with a virtual addressing mechanism, a process for the de-allocation of physical pages sets, by means of a first pointer (ptr) on a line ( 5 ) of a conversion table ( 1 ) that...
|
|
|
6473835 |
Partition of on-chip memory buffer for cache
A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the...
|
|
|
6470437 |
Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design
In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to...
|
|
|
6467026 |
Web cache memory device and browser apparatus utilizing the same
The present invention relates to a cache mechanism of a browser apparatus as a World Wide Web (WWW) client and aims at the improvement of utilization efficiency and the shortening of an information...
|
|
|
6453387 |
Fully associative translation lookaside buffer (TLB) including a least recently used (LRU) stack and implementing an LRU replacement strategy
A memory unit is presented employing a least recently used (LRU) replacement strategy. The memory unit may include a memory subunit for storing data items, circuitry coupled to the memory subunit...
|
|
|
6449692 |
Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure
A computer system ( 8 ) comprising a central processing unit ( 12 ) and a memory hierarchy. The memory hierarchy comprises a first cache memory ( 16 ) and a second cache memory ( 26 ). The first...
|
|
|
6446186 |
Method, apparatus and article of manufacture for mapping physical memory in a virtual address system
A method, apparatus and article of manufacture are provided for minimizing the number of look-ups in a page table entry (PTE) data structure during mapping of virtual addresses to physical...
|
|
|
6446189 |
Computer system including a novel address translation mechanism
A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within...
|
|
|
6442667 |
Selectively powering X Y organized memory banks
This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a...
|
|
|
6438656 |
Method and system for cancelling speculative cache prefetch requests
A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an...
|
|
|
6430657 |
COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUCTION SHOULD BE EXECUTED USING CACHE COHERENCY OR BY EXPORTING THE EXPORTABLE INSTRUCTION, AND EMULATES INSTRUCTIONS SPECIFYING A BUS LOCK
Atomic memory operations are provided by using exportable “fetch and add” instructions and by emulating IA-32 instructions prepended with a lock prefix. In accordance with the present...
|
|
|
6430667 |
Single-level store computer incorporating process-local address translation data structures
An apparatus, program product, and method perform address translation on a process-local, rather than system-wide, basis in a single-level store virtual memory management system using a plurality...
|
|
|
6418521 |
Hierarchical fully-associative-translation lookaside buffer structure
A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB 0 memory having a plurality of entries and a second-level TLB 1 memory operatively...
|
|
|
6418523 |
Apparatus comprising a translation lookaside buffer for graphics address remapping of virtual addresses
A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in...
|
|
|
6418522 |
Translation lookaside buffer for virtual memory systems
The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB 1 and a larger...
|
|
|
6412056 |
Extended translation lookaside buffer with fine-grain state bits
A software distributed shared memory system includes a translation lookaside buffer extended to include fine-grain memory block-state bits associated with each block of information within a page...
|
|
|
6408373 |
Method and apparatus for pre-validating regions in a virtual addressing scheme
A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB)...
|
|
|
6401177 |
Memory system for restructuring a main memory unit in a general-purpose computer
A memory system has a plurality of memory banks, performs interleaving between the memory banks, and structures a memory by dividing into a plurality of memory blocks which are independently...
|