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6779102 |
Data processor capable of executing an instruction that makes a cache memory ineffective
A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the...
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6779049 |
Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of...
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6779085 |
TLB operation based on task-ID
A digital system and method of operation is provided in which several processing resources ( 340 ) and processors ( 350 ) are connected to a shared translation lookaside buffer (TLB) ( 300, 310 ( n...
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6772315 |
Translation lookaside buffer extended to provide physical and main-memory addresses
A processor includes a translation look-aside buffer (TLB) that relates virtual page addresses to both physical page addresses and main-memory addresses. If the processor references a virtual page...
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6772271 |
Reduction of bank switching instructions in main memory of data processing apparatus having main memory and plural memory
A data processing apparatus has a main memory and a plurality of memory banks. A bank switching instruction designating a particular bank address of the first memory bank is stored in an arbitrary...
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6766431 |
Data processing system and method for a sector cache
A data processing system ( 10 ) provides a set of user configurable control bits in a cache control register ( 50 ) that sets a cache fill policy. The data processing system also allows a cache...
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6766434 |
Method for sharing a translation lookaside buffer between CPUs
The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a...
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6763446 |
Systems and methods for handling storage access requests
In general, in one aspect, the description includes a method of responding to storage access requests. The method includes defining at least one write area and at least one read-only area,...
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6760829 |
MMU descriptor having big/little endian bit to control the transfer data between devices
A digital system is provided with a memory ( 506 ) shared by several initiator resources ( 540-550 ), wherein a portion of the initiator resources are big endian and another portion of the...
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6760828 |
Method and apparatus for using logical volume identifiers for tracking or identifying logical volume stored in the storage system
Method and apparatus are disclosed for identifying logical volumes stored among a plurality of storage elements in a computer storage system. A unique logical volume identifier may be assigned to...
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6760787 |
Recoverable methods and systems for processing input/output requests including virtual memory addresses
A recoverable I/O request processor includes computer-executable instructions for processing I/O requests, such as requests to send or receive data through a network. The recoverable I/O request...
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6757806 |
Method for converting addresses in a semiconductor memory device and apparatus therefor
An apparatus for and a method of converting an address in a semiconductor memory device sequentially performing a data write operation on addresses from an upper address, by performing a write or...
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6745306 |
Method and system for restricting the load of physical address translations of virtual addresses
A method and system for protecting data on a computer system uses one or more restricted areas of memory to store proprietary or confidential data. The translation lookaside buffer (TLB) is used to...
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6745284 |
Data storage subsystem including a storage disk array employing dynamic data striping
A data storage subsystem including a storage disk array employing dynamic data striping. A data storage subsystem includes a plurality of storage devices configured in an array and a storage...
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6742103 |
Processing system with shared translation lookaside buffer
A multiprocessor system ( 20, 102, 110 ) uses multiple operating systems or a single operating system uses μTLBs ( 36 ) and a shared TLB subsystem ( 48 ) to provide efficient and flexible...
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6742104 |
Master/slave processing system with shared translation lookaside buffer
A multiprocessor system ( 20, 102, 110 ) uses multiple operating systems or a single operating system uses μTLBs ( 36 ) and a shared TLB subsystem ( 48 ) to provide efficient and flexible...
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6738865 |
Method, system, and program for demoting data from cache based on least recently accessed and least frequently accessed data
Disclosed is a method, system, and program for caching data. Data from a device, such as a volatile memory device or non-volatile storage device, is maintained in entries in a cache. For each entry...
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6738888 |
TLB with resource ID field
A digital system and method of operation is provided in which several processing resources ( 340 ) and processors ( 350 ) are connected to a shared translation lookaside buffer (TLB) ( 300, 310 ( n...
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6732192 |
Disc recording scheme for enabling quick access to disc data
A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical...
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6728962 |
Context swapping in multitasking kernel
Disclosed is context swapping in a multitasking operating system for a processor that includes providing a plurality of context blocks for storing context information for a plurality of processes,...
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6728859 |
Programmable page table access
An apparatus and method are provided to enable programmable page table accesses in a virtual memory system. The apparatus includes context logic and context configuration logic. The context logic...
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6725284 |
Logical partition hosted virtual input/output using shared translation control entries
The present invention provides a method for sharing I/O facilities among logical partitions. A remote translation control entry table is created on a hosted partition appearing to own a virtual...
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6725189 |
Adapter for coupling a legacy operating system to a driver of an I/O channel which has an incompatible native operating system interface
An adapter program couples a legacy operating system to a driver program of an I/O channel which has an incompatible interface to a native operating system. The adapter program includes a...
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6725289 |
Transparent address remapping for high-speed I/O
A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region....
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6715057 |
Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizes
A system and method is disclosed to efficiently translate virtual-to-physical addresses of large size pages of data by eliminating one level of a multilevel page table. A computer system containing...
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6711653 |
Flexible mechanism for enforcing coherency among caching structures
The present invention provides a computer system that is capable of operating in a first or second cache coherency mode according to the operating environment in which the computer system is booted...
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6708265 |
Method and apparatus for moving accesses to logical entities from one storage element to another storage element in a computer storage system
Methods and apparatus are disclosed for moving logical entities from one storage element to another storage element. Movement of the logical entity may be accomplished by using a logical volume...
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6697912 |
Prioritized content addressable memory
A prioritized content addressable memory having an at most one hit property despite the presence of redundant values stored therein. Redundant values within the content addressable memory are...
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6686920 |
Optimizing the translation of virtual addresses into physical addresses using a pipeline implementation for least recently used pointer
A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation...
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6684315 |
Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions
A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional...
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6681313 |
Method and system for fast access to a translation lookaside buffer
In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to...
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6681224 |
Method and device for sorting data, and a computer product
The sorting device comprises a distribution monitoring and cell splitting section which analyzes a distribution of a sort target data group consisting sort target data and obtains an appearance...
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6681312 |
Power saving address translation buffer
In an address translation buffer, multiple content-addressable memories of a first memory array store previous process identifiers for comparing them with a new process identifier to produce a...
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6674441 |
Method and apparatus for improving performance of an accelerated graphics port (AGP) device
A method and apparatus for improving performance of an AGP device is provided. In one embodiment of the invention, a second-level cache is provided for a TLB, and part of the data or part of the...
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6675281 |
Distributed mapping scheme for mass storage system
In accordance with the objectives of the invention a new method is provided for the updating and erasing of flash memory data. The new method effects and improves the write, the update and the read...
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6668314 |
Virtual memory translation control by TLB purge monitoring
In a computer system, an architecture is disclosed for optimizing aspects of data movement operations by performing functions such as memory allocation and notification on hardware rather than...
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6665788 |
Reducing latency for a relocation cache lookup and address mapping in a distributed memory system
An address relocation cache includes a plurality of entries. Each of the plurality of entries is configured to store at least a portion of an input address, at least a portion of an output address...
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6658548 |
System and method in a data processing system for extracting data from a protected region of memory
A system and method for extracting data from a protected region of memory loads at least a first part of extraction code into physical memory and, thereafter, activates a memory mapping facility...
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6651156 |
Mechanism for extending properties of virtual memory pages by a TLB
An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU...
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6643759 |
Mechanism to extend computer memory protection schemes
An apparatus and method are provided that enable a central processing unit (CPU) to extend the protection schemes afforded to virtual memory beyond that which an existing translation lookaside...
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6643756 |
System and method for accessing video data using a translation client
A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The...
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6640296 |
Data processing method and device for parallel stride access
A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable...
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6636925 |
Bus interface circuit preparation apparatus and recording medium
An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware...
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6633957 |
Maximizing sequential read streams while minimizing the impact on cache and other applications
In a data storage system a number of records are prefetched from large volume storage devices for transfer to a cache in order to return requested records to a host computer in response to a read...
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6633967 |
Coherent translation look-aside buffer
The invention is a coherent translation look-aside buffer (TLB) for use in an input/output (I/O) bridge of a symmetrical multiprocessing (SMP) system. The contents of the TLBs may be kept in one of...
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6629229 |
Message index descriptor
A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a...
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6629199 |
DIGITAL DATA STORAGE SYSTEM INCLUDING DIRECTORY FOR EFFICIENTLY PROVIDING FORMATTING INFORMATION FOR STORED RECORDS AND UTILIZATION OF A CHECK VALUE FOR VERIFYING THAT A RECORD IS FROM A PARTICULAR STORAGE LOCATION
A digital data storage system in the form of a mass storage subsystem in which information is stored on one or more disk storage units, with a storage element constituting a track on a disk storage...
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6625713 |
Memory controller and method for managing a logical/physical address control table
A memory controller for reading data stored in a nonvolatile memory that includes a number of erasable blocks containing a number of pages. A logical/physical address control table stored in a...
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6625715 |
System and method for translation buffer accommodating multiple page sizes
A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to...
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6622211 |
Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty
A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the...
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