Sign up


Match Document Document Title
8275963 Asynchronous memory move across physical nodes with dual-sided communication  
A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node...
8275971 Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities  
A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss...
8275884 Method and system for securely sharing content  
A method and apparatus for securely sharing content are provided, which can securely share the content without allowing access by unauthorized third parties. The method of securely sharing content...
8271711 Program status detecting apparatus and method  
A method for a computer including a processor that is capable of counting invalidation of translation lookaside buffers and generating an interrupt at the occurrence of the invalidation, the...
8271750 Entry replacement within a data store using entry profile data and runtime performance gain data  
A data processing system includes a data store having storage locations storing entries which can be used for a variety of purposes, such as operand value prediction, branch prediction, etc. An...
8266370 Method for processing data of flash memory by separating levels and flash memory device thereof  
The present invention discloses a method for processing data of a flash memory by differentiating levels, which includes steps of separating the communication between a host and a flash memory by a...
8250334 Providing metadata in a translation lookaside buffer (TLB)  
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA)...
8250333 Mapping address table maintenance in a memory device  
A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and...
8250578 Pipelining hardware accelerators to computer systems  
A method of pipelining hardware accelerators of a computing system includes associating hardware addresses to at least one processing unit (PU) or at least one logical partition (LPAR) of the...
8250330 Memory controller having tables mapping memory addresses to memory modules  
A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each...
8250440 Address generation checking  
A method for address generation checking including receiving a starting memory address for a data, an ending memory address for the data, a length value of the data, and an address wrap indicator...
8244978 IOMMU architected TLB support  
Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and...
8245003 Composite memory device, data processing method and data processing program  
A composite memory device, a data processing method and a data processing program can efficiently and selectively use a nonvolatile solid-state memory and a recording medium. The composite medium...
8239652 Data processing system  
Before arbitration is performed in an arbitration section, an access from a master is kept in a waiting state until update of a conversion table buffer is performed, and an address conversion...
8234642 Filtering processor requests based on identifiers  
Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the...
8234407 Network use of virtual addresses without pinning or registration  
A system comprising a compute node and coupled network adapter (NA) that allows the NA to directly use CPU virtual addresses without pinning pages in system memory. The NA performs memory accesses...
8225071 Accessing multiple page tables in a computer system  
A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a...
8219776 Logical-to-physical address translation for solid state disks  
Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a...
8219722 DMA and graphics interface emulation  
An emulator schedules emulation threads for DMA emulation and other emulation functions in a time-multiplexed manner. Emulation threads are selected for execution according to a load balancing...
8219755 Fast hit override  
In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag...
8219780 Mitigating context switch cache miss penalty  
Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a...
8214343 Purposing persistent data through hardware metadata tagging  
Storage devices can maintain metadata on a per-block basis, enabling the storage device, the file system, or other higher-level software to store and obtain information about individual blocks of...
8209488 Techniques for prediction-based indirect data prefetching  
A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a...
8209473 Flash storage device and operating method thereof  
The invention also provides a flash storage device. In one embodiment, the flash storage device is coupled to a host, and comprises a random access memory and a controller. The random access memory...
8205030 Composite type recording apparatus, data writing method and data writing program  
There is provided a composite type recording apparatus restricting write operations depending on the type of a connected host apparatus, including a recording medium having a first data region, a...
8195916 Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode  
An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation...
8195915 Mechanism for visualizing memory fragmentation  
A method, system and computer program product for visualizing memory fragmentation in a data processing system includes determining a mobility status of plural memory pages and generating a map...
8195917 Extended page size using aggregated small pages  
A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size,...
8190853 Calculator and TLB control method  
A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro...
8185689 Processor with compare operations based on any of multiple compare data segments  
A method may include, in response to a single command and an N-bit segment value, generating a search key comprising M segments for at least one of a plurality of different databases, the N-bit...
8180953 Data accessing method for flash memory, and storage system and controller system thereof  
A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving...
8176295 Logical-to-physical address translation for a removable data storage device  
A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory...
8171255 Optimization of paging cache protection in virtual environment  
A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for...
8171200 Serially indexing a cache memory  
A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first...
8166276 Translate and verify instruction for a processor  
In an embodiment, a first instruction is defined that comprises at least a first operand from which the execution core is configured to determine a virtual address and a second operand that...
8161243 Address translation caching and I/O cache performance improvement in virtualized environments  
Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by...
8161246 Prefetching of next physically sequential cache line after cache line that includes loaded page table entry  
A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load...
8156305 Remapping of data addresses for large capacity low-latency random read memory  
Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses...
8156309 Translation look-aside buffer with variable page sizes  
Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the...
8145876 Address translation with multiple translation look aside buffers  
A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first...
8140820 Data processing apparatus and method for handling address translation for access requests issued by processing circuitry  
A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce,...
8140822 System and method for maintaining page tables used during a logical partition migration  
Maintaining data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target...
8140823 Multithreaded processor with lock indicator  
Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a...
8135914 Managing cache data and metadata  
Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache...
8127072 Data storage device and method for accessing flash memory  
The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an...
8117422 Fast address translation for linear and circular modes  
The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address...
8117420 Buffer management structure with selective flush  
A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a...
8108650 Translation lookaside buffer (TLB) with reserved areas for specific sources  
In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may...
8103850 Dynamic translation in the presence of intermixed code and data  
A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate...
8099581 Synchronizing a translation lookaside buffer with an extended paging table  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...