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7917725 |
Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer
A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory...
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7913057 |
Translation lookaside buffer checkpoint system
A system that, at a process checkpoint, pauses the process to copy the system state for the process and then copies pages of the process in memory to disk storage while the process continues to...
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RE42213 |
Dynamic reconfigurable memory hierarchy
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management...
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7904678 |
Technique for recovering mirror consistency in cooperative virtual storage
Disclosed is a method implementable by a computer system for maintaining consistency between mirrors of a mirrored data volume. In one embodiment, the method includes the computer system generating...
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7900017 |
Mechanism for remapping post virtual machine memory pages
According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates...
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7895410 |
Method and apparatus for facilitating adaptive page sizes
One embodiment of the present invention provides a system and a method for performing a page-table lookup in a manner that supports adaptive page sizes. During operation, the system receives a...
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7890632 |
Load balancing using replication delay
A method, system, and computer usable program product for load balancing using replication delay are provided in the illustrative embodiments. In response to a request to update, a system updates...
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7890673 |
System and method for accessing non processor-addressable memory
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs,...
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7886127 |
Methods for accessing multiple page tables in a computer system
A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a...
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7882330 |
Virtualizing an IOMMU
In one embodiment, a system comprises one or more input/output (I/O) devices; an I/O memory management unit (IOMMU) coupled to receive memory requests sourced by the I/O devices and configured to...
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7877504 |
Techniques for entry lookups
Techniques to store entries so that minimal sequential memory accesses are used to determine all relevant entries. Entries may be grouped into blocks. The order of entries within blocks may be set...
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7873961 |
Supervisory operating system for running multiple child operating systems simultaneously and optimizing resource usage
A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of...
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7873711 |
Method, system and program product for managing assignment of MAC addresses in a virtual machine environment
A method, system and program product for managing assignment of virtual physical addresses. The method includes requesting, using a services function provided by a virtual machine operating system,...
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7873792 |
Prefetching in a virtual memory system based upon repeated accesses across page boundaries
A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a...
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7865675 |
Controlling cleaning of data values within a hardware accelerator
A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware...
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7840850 |
Data processing system for logging memory access data
A data processing system for logging memory access data; the data processing system having a memory management unit to support a virtual memory environment having a first data structure to store...
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7840617 |
Host device and memory system
A memory system includes a nonvolatile semiconductor memory and a controller which controls the semiconductor memory, the memory system being inserted into the host device. The host device further...
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7840776 |
Translated memory protection apparatus for an advanced microprocessor
A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps...
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7836242 |
Method for page random write and read in blocks of flash memory
A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with...
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7831760 |
Serially indexing a cache memory
A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first...
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7822942 |
Selectively invalidating entries in an address translation cache
An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each...
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7822926 |
Cache memory
A data processor includes a cache memory having a plurality of cache rows each row storing a cache line of data values, a memory management unit responsive to a page table entry to control access...
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7822943 |
Microprocessor with improved data stream prefetching using multiple transaction look-aside buffers (TLBs)
Systems, methods and computer program products for improving data stream prefetching in a microprocessor are described herein. The method includes the steps of: 1) translating an address associated...
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7818520 |
Method of specifying access sequence of a storage device
The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access...
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7814287 |
Using writeable page tables for memory address translation in a hypervisor environment
A method and system for using writeable page tables to increase performance of memory address translation in computing environments utilizing a hypervisor. Guest operating systems are given...
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7814292 |
Memory attribute speculation
A technique to speculatively assign a memory attribute. More specifically, embodiments of the invention include an architecture to assign and issue a speculative memory attribute based on a...
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7814267 |
Processor with compare operations based on any of multiple compare data segments
A processor device integrated circuit can include a plurality of storage locations logically configurable into at least one database. Such a database can include a number of records, record having...
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7809921 |
Method and apparatus for translating a virtual address to a real address using blocks of contiguous page table entries
A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to...
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7809922 |
Translation lookaside buffer snooping within memory coherent system
A node of a multiple-node system includes a translation lookaside buffer (TLB), a cache, and a TLB snoop mechanism. The node shares memory with other nodes of the multiple-node systems, and is...
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7809859 |
Network switching device and control method of network switching device
A network switching device includes multiple ports, multiple switching processors, and a table manager. The switching processors respectively have an address table, a output port specification...
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7809888 |
Content-aware caching techniques
A caching technique involves receiving a cache request to move data into a cache (or a particular cache level of a cache hierarchy), and generating a comparison between content of the data and...
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7809923 |
Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU)
In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to...
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7805588 |
Caching memory attribute indicators with cached memory data field
A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a...
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7797509 |
Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure
Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of...
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7797510 |
Memory management for virtual address space with translation units of variable range size
In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address...
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7793070 |
Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics
A processing system includes memory management software responsive to a translation lookaside buffer miss. The memory management software updates translation lookaside buffer information based on...
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7788464 |
Scalability of virtual TLBs for multi-processor virtual machines
Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters;...
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7783838 |
Maintaining coherency of derived data in a computer system
A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer...
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7783858 |
Reducing memory overhead of a page table in a dynamic logical partitioning environment
Mechanisms for reducing memory overhead of a page table in a dynamic logical partitioning (LPAR) environment are provided. Each LPAR, upon its creation, is allowed to declare any maximum main...
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7783859 |
Processing system implementing variable page size memory organization
A processing system includes memory management software responsive to changes in a page table. The memory management software consolidates contiguous page table entries into one or more page table...
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7779226 |
Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory
There is disclosed a controller included in a flash memory system attachable to a memory interface of a host system. The controller performs a process for minimizing the maximum number of defective...
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7774658 |
Method and apparatus to search for errors in a translation look-aside buffer
A method and apparatus for discovering errors in a translation look-aside buffer (TLB). The TLB comprises a content addressable memory (CAM) and a random access memory (RAM). The TLB contains...
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7761676 |
Protecting memory by containing pointer accesses
In one embodiment, the present invention includes a method for associating a first identifier with a first pointer that points to a first object in a memory. The first identifier may correspond to...
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7761686 |
Address translator and address translation method
An address translator capable of reducing system loads in address translation and an overhead in switching between operating systems. A plurality of address translation buffers classifies and...
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7761497 |
Storage medium having a manageable file directory structure
A file-mapping method and system can better manage the number of items (i.e., files, subdirectories, or a combination of them) within any single directory within a storage medium. The method and...
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7739477 |
Multiple page size address translation incorporating page size prediction
Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation...
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7739476 |
R and C bit update handling
In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to...
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7739466 |
Method and apparatus for supporting immutable memory
A method for managing a memory in a computer system is disclosed. A mapping of a virtual page to physical page is locked in response to receiving a request to make the page immutable. According to...
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7734890 |
Method and system for using a distributable virtual address space
A method and system are disclosed for using a distributable virtual address space. According to an exemplary embodiment, a method for using a distributable virtual address space includes providing...
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7730278 |
Chunk-specific executable code for chunked java object heaps
A mechanism is disclosed for storing one or more chunk-specific sets of executable instructions at one or more predetermined offsets within chunks of a chunked heap. The mechanism provides for...
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