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8195916 Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode  
An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation...
8195915 Mechanism for visualizing memory fragmentation  
A method, system and computer program product for visualizing memory fragmentation in a data processing system includes determining a mobility status of plural memory pages and generating a map...
8195917 Extended page size using aggregated small pages  
A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size,...
8190853 Calculator and TLB control method  
A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro...
8185689 Processor with compare operations based on any of multiple compare data segments  
A method may include, in response to a single command and an N-bit segment value, generating a search key comprising M segments for at least one of a plurality of different databases, the N-bit...
8180953 Data accessing method for flash memory, and storage system and controller system thereof  
A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving...
8176295 Logical-to-physical address translation for a removable data storage device  
A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory...
8171255 Optimization of paging cache protection in virtual environment  
A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for...
8171200 Serially indexing a cache memory  
A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first...
8166276 Translate and verify instruction for a processor  
In an embodiment, a first instruction is defined that comprises at least a first operand from which the execution core is configured to determine a virtual address and a second operand that...
8161243 Address translation caching and I/O cache performance improvement in virtualized environments  
Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by...
8161246 Prefetching of next physically sequential cache line after cache line that includes loaded page table entry  
A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load...
8156305 Remapping of data addresses for large capacity low-latency random read memory  
Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses...
8156309 Translation look-aside buffer with variable page sizes  
Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the...
8145876 Address translation with multiple translation look aside buffers  
A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first...
8140820 Data processing apparatus and method for handling address translation for access requests issued by processing circuitry  
A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce,...
8140822 System and method for maintaining page tables used during a logical partition migration  
Maintaining data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target...
8140823 Multithreaded processor with lock indicator  
Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a...
8135914 Managing cache data and metadata  
Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache...
8127072 Data storage device and method for accessing flash memory  
The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an...
8117422 Fast address translation for linear and circular modes  
The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address...
8117420 Buffer management structure with selective flush  
A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a...
8108650 Translation lookaside buffer (TLB) with reserved areas for specific sources  
In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may...
8103850 Dynamic translation in the presence of intermixed code and data  
A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate...
8099581 Synchronizing a translation lookaside buffer with an extended paging table  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
8094158 Using programmable constant buffers for multi-threaded processing  
Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has...
8095773 Dynamic address translation with translation exception qualifier  
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of...
8086438 Method and system for instruction-set architecture simulation using just in time compilation  
A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at...
8082416 Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure  
Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of...
8078792 Separate page table base address for minivisor  
In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be...
8078806 Microprocessor with improved data stream prefetching  
A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch...
8074047 System and method for content replication detection and elimination in main memory  
A system and method for effectively increasing the amount of data that can be stored in the main memory of a computer, particularly, by a hardware enhancement of a memory controller apparatus that...
8041876 Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine  
A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host...
8041887 Memory device and control method thereof  
A control method of a memory device including a storage area formed of a nonvolatile semiconductor memory, includes updating a file stored in the storage area by using a file system which supports...
8037281 Miss-under-miss processing and cache flushing  
Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests...
8032716 System, method and computer program product for providing a new quiesce state  
A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce...
8032707 Managing cache data and metadata  
Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache...
8028120 System with flash memory device and data recovery method thereof  
A method is for recovering a block mapping table in a system including a flash memory device, where the block mapping table utilizes address mapping in accordance with a wear-leveling scheme. The...
8028132 Collision handling apparatus and method  
The present invention relates to mechanisms for handling and detecting collisions between threads (5, 6, 7) that execute computer program instructions out of program order. According to an...
8028118 Using an index value located on a page table to index page attributes  
Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According...
8024506 Maintaining address translations during the software-based processing of instructions  
The invention is used in a virtual machine monitor for a multiprocessing system that includes a virtual memory system. During a software-based processing of a guest instruction, including...
8024547 Virtual memory translation with pre-fetch prediction  
A system to facilitate virtual page translation. An embodiment of the system includes a processing device, a front end unit, and address translation logic. The processing device is configured to...
8019964 Dynamic address translation with DAT protection  
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a...
8019962 System and method for tracking the memory state of a migrating logical partition  
An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the...
8019968 3-dimensional L2/L3 cache array to hide translation (TLB) delays  
Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data...
8010770 Caching device for NAND flash translation layer  
A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary...
8001315 Memory device and control method thereof  
A control method of a memory device including a storage area formed of a nonvolatile semiconductor memory, includes updating a file stored in the storage area by using a file system which supports...
7996649 Translation look-aside buffer with look-up optimized for programmable logic resource utilization  
A dual-port block random access memory (BRAM) can include first and second sections including direct mapped cache entries. The dual-port BRAM further can include third and fourth sections including...
7996650 Microprocessor that performs speculative tablewalks  
A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect...
7991977 Advanced processor translation lookaside buffer management in a multithreaded system  
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and...