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8433855 Serializing translation lookaside buffer access around address translation parameter modification  
Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable...
8429376 Translation look-aside buffer  
A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may...
8429377 Optimizing TLB entries for mixed page size storage in contiguous memory  
A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises...
8417915 Alias management within a virtually indexed and physically tagged cache memory  
A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12...
8417893 Memory mapping techniques  
Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some...
8417913 Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages  
A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to...
8412911 System and method to invalidate obsolete address translations  
A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated...
8407422 Address translation caching and I/O cache performance improvement in virtualized environments  
Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by...
8407450 Electronic device, time difference data acquisition method, and data structure for time difference data  
An electronic device receives satellite signals from positioning information satellites and acquires positioning information and time information. A stored data table comprises a first block of...
8407449 Non-volatile semiconductor memory storing an inverse map for rebuilding a translation table  
A non-volatile semiconductor memory is disclosed comprising a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a...
8402247 Remapping of data addresses for large capacity low-latency random read memory  
Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses...
8397050 Simulator and simulating method for running guest program in host  
A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table...
8397049 TLB prefetching  
In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB...
8397027 Methods and systems for multi-caching  
Provided are methods and systems for multi-caching. The methods and systems provided can enhance network content delivery performance in terms of reduced response time and increased throughput,...
8392690 Management method for reducing utilization rate of random access memory (RAM) used in flash memory  
A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed...
8392629 System and methods for using a DMA module for a plurality of virtual machines  
A system comprising a plurality of virtual machines executed by a computing system; and an adapter; wherein the adapter includes a direct memory access (DMA) module for transferring control blocks...
8386745 I/O memory management unit including multilevel address translation for I/O and computation offload  
An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate...
8386748 Address translation unit with multiple virtual queues  
An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store...
8386749 Address mapping in virtualized processing system  
A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated...
8386747 Processor and method for dynamic and selective alteration of address translation  
Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit...
8380894 I/O mapping-path tracking in a storage configuration  
A system, method and program product for tracking an I/O mapping-path among a plurality of nodes in a storage configuration. A system is disclosed that includes: a path tracking manager...
8380951 Dynamically updating backup configuration information for a storage cluster  
Various embodiments of a system and method for updating backup configuration information used by backup software to perform backup operations for a storage cluster are described. Backup...
8370575 Optimized software cache lookup for SIMD architectures  
Process, cache memory, computer product and system for loading data associated with a requested address in a software cache. The process includes loading address tags associated with a set in a...
8370602 Method for memory space management  
A method for memory space management is disclosed. It uses a resident program loaded into an operation system or the controller of a storage device to monitor the storage space and the resource...
8370604 Method and system for caching attribute data for matching attributes with physical addresses  
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
8364933 Software assisted translation lookaside buffer search mechanism  
A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry...
8358152 Integrated circuit including pulse control logic having shared gating control  
An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal....
8356158 Mini-translation lookaside buffer for use in memory translation  
One or more methods and systems of improving performance and reducing the size of a translation lookaside buffer are presented. In one embodiment, the method comprises using a bit obtained from a...
8352715 Method for booting up a mobile phone quickly and the mobile phone thereof  
A method for booting up a mobile phone quickly is disclosed. The method includes the steps of: driving hardware devices when the mobile phone is turned on; initializing application software...
8352706 Memory system managing address translation table and method of controlling thereof  
A forward lookup address translation table and a reverse lookup address translation table stored in a nonvolatile second storing unit are transferred as a master table to a volatile first storing...
8347064 Memory access techniques in an aperture mapped memory space  
A method of accessing memory, in accordance with one embodiment, includes receiving a memory access request that includes a virtual address. An address of a given page table is determined...
8341609 Code generation in the presence of paged memory  
A computer is programmed to automatically identify multiple sequences of executable code such that each sequence fits within a page of memory. When the executable code comprising several sequences...
8341379 R and C bit update handling  
In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to...
8341329 Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine  
A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host...
8341316 Method and apparatus for controlling a translation lookaside buffer  
A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions...
8341380 Efficient memory translator with variable size cache line coverage  
One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address...
8335908 Data processing apparatus for storing address translations  
Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup...
8332614 System, method and computer program product for providing a programmable quiesce filtering register  
Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a...
8327112 Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer  
A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a...
8316212 Translation lookaside buffer (TLB) with reserved areas for specific sources  
In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may...
8316211 Generating multiple address space identifiers per virtual machine to switch between protected micro-contexts  
Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes...
8312461 System and method for discovering and protecting allocated resources in a shared virtualized I/O device  
A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO)...
8312210 Apparatus, system, and method for storing and retrieving compressed data  
An apparatus, system, and method are disclosed for storing and retrieving compressed data. A compression module compresses a data file organized in logical tracks. A ratio module determines a...
8301865 System and method to manage address translation requests  
A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the...
8296546 Synchronizing a translation lookaside buffer with an extended paging table  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
8296518 Arithmetic processing apparatus and method  
An apparatus includes a TLB storing a part of a TSB area included in a memory accessed by the apparatus. The TSB area stores an address translation pair for translating a virtual address into a...
8296547 Loading entries into a TLB in hardware via indirect TLB entries  
An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given...
8285933 Avoiding use of an inter-unit network in a storage system having multiple storage control units  
A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system...
8285969 Reducing broadcasts in multiprocessors  
Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation...
8275598 Software table walk during test verification of a simulated densely threaded network on a chip  
A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test...