|
Match
|
Document |
Document Title |
|
|
4456958 |
System and method of renaming data items for dependency free code
A mechanism for a data processor that is adapted to receive strings of object code, form them into higher level tasks and to determine sequences of such tasks which are logically independent so...
|
|
|
4456954 |
Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations
Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables...
|
|
|
4453230 |
Address conversion system
An address conversion system comprises an improved associative memory circuit for providing a real address corresponding to an applied virtual address with reference to the correspondence between...
|
|
|
4410941 |
Computer having an indexed local ram to store previously translated virtual addresses
A multitasking data processing machine supports virtual memory comprising a plurality of segments, and has physical memory comprising relatively fast main memory and relatively slow secondary...
|
|
|
4395754 |
Data processing system having virtual memory addressing
A data processing system has virtual memory addressing and includes a buffer between the working memory and the central processor. The buffer includes a data buffer divided into a plurality of...
|
|
|
4393443 |
Memory mapping system
A circuit for enhancing the performance of a random-access-memory-based memory expansion system is disclosed. Memory capacity and a control register are added to the traditional memory mapping...
|
|
|
4386402 |
Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
The processor's interrupt stack memory and cache memory share a common data memory and are accessed using virtual addresses. A separate address translation buffer (ATB) is used for both the...
|
|
|
4376297 |
Virtual memory addressing device
A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses...
|
|
|
4373179 |
Dynamic address translation system
A dynamic address translation system for use in a channel or sub-system adapter, wherein the main memory of a system is used in common with a central processing unit. The system provides registers...
|
|
|
4355355 |
Address generating mechanism for multiple virtual spaces
The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The...
|
|
|
4354225 |
Intelligent main store for data processing systems
A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and...
|
|
|
4347565 |
Address control system for software simulation
An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated,...
|
|
|
4326248 |
Multiple virtual storage control system
A multiple virtual storage control system for a data processing system for handling a plurality of virtual spaces is disclosed. Virtual addresses indicative of addresses in the virtual spaces are...
|
|
|
4290104 |
Computer system having a paging apparatus for mapping virtual addresses to real addresses for a memory of a multiline communications controller
A paging apparatus includes addressing hardware for addressing a number of physical devices coupled to various communication buses, for mapping virtual addresses to real addresses, and controlling...
|
|
|
4241401 |
Virtual address translator utilizing interrupt level code
Apparatus for use within a virtual memory data processing system offering a way of protecting data used at one interrupt level state from unauthorized use at another interrupt level state. A...
|
|
|
4218743 |
Address translation apparatus
Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses...
|
|
|
4188662 |
Address converter in a data processing apparatus
An address converter according to the present invention is provided with an adddress conversion table, and can store a single logical address, a single physical address, a plurality of logical...
|
|
|
4170039 |
Virtual address translation speed up technique
Address translation apparatus is provided where the address to be translated is compared with two address translation candidates sequentially. The virtual address to be translated is contained in a...
|
|
|
4163280 |
Address management system
An address management system includes a central processing unit (CPU) and an address management unit arranged between a direct memory device (DMA) and a main memory unit to control memory access...
|
|
|
4136385 |
Synonym control means for multiple virtual storage systems
The embodiments relate to special controls in a processor which eliminate synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently...
|
|
|
4096573 |
DLAT Synonym control means for common portions of all address spaces
The embodiment relates to special controls in a processor to prevent synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate...
|
|
|
4068303 |
Address translation managing system with translation pair purging
In a data processing system employing a virtual storage system, a plurality of address translation pairs each consisting of a logical address in a virtual storage space and a real address in a real...
|
|
|
4064558 |
Method and apparatus for randomizing memory site usage
A method for randomly scrambling the physical address of a block of data, within a memory subject to data site deterioration, by utilizing an auxiliary correspondence memory to pair each logical...
|
|
|
4057848 |
Address translation system
In an electronic computer employing virtual storage system, the mapping of plural logical spaces -- logical addressing capability -- onto larger real space is made possible so that a conventional...
|
|
|
4053948 |
Look aside array invalidation mechanism
A virtual memory system is described in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory...
|
|
|
4037209 |
Data processing system for converting from logical addresses to physical addresses
An address converter for converting logical addresses of a program to physical addresses of a memory device comprises a first address converter having entries corresponding to the logical addresses...
|
|
|
4010451 |
Data structure processor
Data processing apparatus, particularly for use with a computer, is described which includes a primary store and an address translator. The primary store which has a fast access time compared with...
|
|
|
4004278 |
System for switching multiple virtual spaces
In a virtual memory system capable of embodying therein multiple virtual spaces used in a switching mode and having a high speed memory for storing address sets each including a virtual address of...
|
|
|
3902164 |
Method and means for reducing the amount of address translation in a virtual memory data processing system
In a data processing system including an associative store for rapid translation of recently used virtual page addresses to corresponding real page addresses to access main store, an additional...
|
|
|
3902163 |
Buffered virtual storage and data processing system
Disclosed is a data processing system which operates with multi-programming and virtual storage. Logical addresses are translated to real addresses by use of translation tables stored in main...
|
|
|
3839706 |
INPUT/OUTPUT CHANNEL RELOCATION STORAGE PROTECT MECHANISM
An input/output data channel operates in conjunction with a virtual memory computer. A channel operation is commenced with the execution of a start I/O instruction which transfers a channel address...
|
|
|
3829840 |
VIRTUAL MEMORY SYSTEM
This specification describes a virtual memory system comprising a main storage and a smaller high speed buffer. Both main storage and the buffer are real-address oriented. Current virtual-to-real...
|
|
|
3800286 |
ADDRESS DEVELOPMENT TECHNIQUE UTILIZING A CONTENT ADDRESSABLE MEMORY
A content addressable memory is disclosed which provides for fast address development in a relatively addressed data processing system. The content addressable memory includes an associative...
|
|
|
3781808 |
VIRTUAL MEMORY SYSTEM
This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual...
|
|
|
3768080 |
DEVICE FOR ADDRESS TRANSLATION
In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to...
|
|
|
3764996 |
STORAGE CONTROL AND ADDRESS TRANSLATION
A virtual memory system comprising a main storage and a smaller high speed buffer. Current virtual-to-real address translations for both the main storage and the buffer are retained in a Storage...
|
|
|
3761881 |
TRANSLATION STORAGE SCHEME FOR VIRTUAL MEMORY SYSTEM
A virtual memory system comprising a main storage and a smaller high speed buffer. Both main storage and the buffer are real-address-oriented. Current virtual-to-real address translations are...
|
|
|
3723976 |
MEMORY SYSTEM WITH LOGICAL AND REAL ADDRESSING
A memory system is disclosed for use in a multiprocessing environment where each processor has associated with it a buffer memory and means are provided for one buffer to retain a modified copy of...
|
|
|
3693165 |
PARALLEL ADDRESSING OF A STORAGE HIERARCHY IN A DATA PROCESSING SYSTEM USING VIRTUAL ADDRESSING
A data processing system includes a central processing unit which uses virtual addressing in address control words to access a high speed buffer store of limited storage capacity and simultaneously...
|
|
|
3387272 |
Content addressable memory system using address transformation circuits
|
|
|
3323108 |
Symbolic addressing
|
|
|
3082406 |
Decoding device
|