|
Match
|
Document |
Document Title |
|
|
5784709 |
Translating buffer and method for translating addresses utilizing invalid and don't care states
A translation buffer and method for translating a virtual address to a physical address are disclosed. The translation buffer includes a plurality of storage locations, each including a tag store...
|
|
|
5764944 |
Method and apparatus for TLB invalidation mechanism for protective page fault
A method and apparatus for modifying protective page fault, which executes TLB table walk when protective page fault occurs in order to modify protective page fault. The method includes the...
|
|
|
5765192 |
Method and computer program product to reuse directory search handles
A method is disclosed for reusing directory search handles in a manner that minimizes the possibility that a handle allocated for a directory search request that is not yet complete will be reused....
|
|
|
5765209 |
Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages
The present invention relates to computer systems utilizing a TLB with variable sized pages. This invention detects conflicts between address tags stored in the TLB and a prospective address tag....
|
|
|
5765201 |
Changing page size in storage media of computer system
When a computer system is upgraded, such as by adding a more advanced processor chip and/or a new operating system, a different page size may be employed. The page size is altered for data...
|
|
|
5761694 |
Multi-bank memory system and method having addresses switched between the row and column decoders in different banks
A memory subsystem with multiple memory banks each having an array of memory cells includes address control circuitry for presenting address bits to the row and column decoders of the memory banks...
|
|
|
5754818 |
Architecture and method for sharing TLB entries through process IDS
An address translation control circuit which operates in connection with a processor and a translation look-aside buffer ("TLB") to perform virtual-to-physical address translations through shared...
|
|
|
5752275 |
Translation look-aside buffer including a single page size translation unit
A method and apparatus for use in a computer system to translate virtual addresses into translated addresses. According to one aspect of the invention, a dynamically configurable translation unit...
|
|
|
5751990 |
Abridged virtual address cache directory
A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by...
|
|
|
5734858 |
Method and apparatus for simulating banked memory as a linear address space
A method and apparatus for providing access to a banked peripheral memory via a contiguous linear address space. The present invention provides a linear address space having a present region that...
|
|
|
5729711 |
Data driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writings
The system includes a data driven processor, a main memory, a cache memory and a memory access unit for accessing the cache memory, the main memory or both and for maintaining the contents of the...
|
|
|
5727179 |
Memory access method using intermediate addresses
In an access method, with which a first processor in a first processor unit can access a memory in a second processor unit in a multi-processor system, a virtual address generated by the first...
|
|
|
5724541 |
Apparatus and method for randomly accessing sequential access storage
An information storage device randomly accesses data items in a sequential access storage medium. A controller, upon loading of the sequential access storage medium, causes the blocks of data items...
|
|
|
5724538 |
Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer
The present invention relates to the design of computer systems incorporating virtual memory where a virtual page number is longer than the inherent basic data width of the designed computer...
|
|
|
5721858 |
Virtual memory mapping method and system for memory management of pools of logical partitions for bat and TLB entries in a data processing system
A method and system for memory management and address translation mapping of pools of logical partitions for BAT and TLB entries in a data processing system is provided. An entry in an address...
|
|
|
5717885 |
TLB organization with variable page size mapping and victim-caching
A translation look-aside buffer (TLB) for translating a variable page size virtual page number to a physical page number. The TLB partitions the virtual page number into an upper portion and a...
|
|
|
5713998 |
Method for producing high opacifying kaolin pigment
An improvement is disclosed applicable to the method for producing a calcined kaolin by the steps of wet beneficiating a crude kaolin to form a slurry of the beneficiated kaolin; dewatering the...
|
|
|
5699543 |
Profile guided TLB and cache optimization
A method and an apparatus for profile guided TLB's (translation look-aside buffer) and cache optimization in an operating system. A typical operating system has a working set of information for any...
|
|
|
5699551 |
Software invalidation in a multiple level, multiple cache system
A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a...
|
|
|
5696927 |
Memory paging system and method including compressed page mapping hierarchy
A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside...
|
|
|
5696925 |
Memory management unit with address translation function
Memory management unit with address translation function improves the translation speed for virtual addresses and minimizes the deviation in response time. The memory management unit translates...
|
|
|
5684993 |
Segregation of thread-specific information from shared task information
A multi-processor system includes memory and at least two central processing units (CPUs) that may execute different threads of computation of a same task at the same time. CPU-specific data is...
|
|
|
5682495 |
Fully associative address translation buffer having separate segment and page invalidation
A fully associative address translator which includes a number of entries, each of said number of entries translating a received effective address into a real address, each received effective...
|
|
|
5680566 |
Lookaside buffer for inputting multiple address translations in a computer system
A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in...
|
|
|
5675763 |
Cache memory system and method for selectively removing stale aliased entries
A cache memory system and method for selectively removing stale "aliased" entries, which arise when portions of several address spaces are mapped into a single region of real memory, from a...
|
|
|
5668968 |
Two-level virtual/real set associative cache system and method with improved synonym detection
A two-level virtual/real cache system, and a method for detecting and resolving synonyms in the two-level virtual/real cache system, are described. Lines of a first level virtual cache are tagged...
|
|
|
5666509 |
Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof
A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers...
|
|
|
5664139 |
Method and a computer system for allocating and mapping frame buffers into expanded memory
A video driver in a computer system is used to map a large video frame buffer into the logical address space above physical memory while the computer system is operating in WINDOWS STANDARD mode....
|
|
|
5664217 |
Method of avoiding physical I/O via caching with prioritized LRU management
A method of caching I/O requests permits caching in the MVS environment independent of the access method protocol used to initiate an I/O request (e.g., QSAM, VSAM, Media Manager). In addition,...
|
|
|
5664159 |
Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register
A single breakpoint address register on a CPU is shared to emulate a plurality of breakpoint registers. A plurality of breakpoints are stored in an emulation area of main memory. One of these...
|
|
|
5659697 |
Translation lookaside buffer for faster processing in response to availability of a first virtual address portion before a second virtual address portion
A processing system and method of operation are provided. First translation information is stored. A logic state of a first match line is selectively modified in response to a comparison between...
|
|
|
5652872 |
Translator having segment bounds encoding for storage in a TLB
A computer system emulates segment bounds checking with a paging system. Pages entirely within a segment are designated as `clear pages`, while the first and last pages containing segment bounds...
|
|
|
5649155 |
Cache memory accessed by continuation requests
In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a...
|
|
|
5644748 |
Processor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacing
An index buffer circuit and a translation look-aside buffer (TLB) are provided in an address unit of a vector processor unit. The index buffer circuit incudes a plurality of buffers, an input...
|
|
|
5634009 |
Network data collection method and apparatus
Disclosed are a method and apparatus for collecting network data from a computer network. Control structures are created for groups of data to be collected. The control structures are then...
|
|
|
5630088 |
Virtual to physical address translation
A high-speed address translation look-aside buffer (TLB) for translating an explicit address, comprised of an index, a TLB index, and an offset, into a physical address. The TLB cooperates with a...
|
|
|
5630087 |
Apparatus and method for efficient sharing of virtual memory translations
A method and apparatus to share virtual memory translations in a computer is described. The apparatus includes an operating system that runs in conjunction with a central processing unit. The...
|
|
|
5628023 |
Virtual storage computer system having methods and apparatus for providing token-controlled access to protected pages of memory via a token-accessible view
A virtual storage computer system having token controlled storage protection. The computer system includes a processor, a real storage, and a virtual storage containing a user space and a system...
|
|
|
5619672 |
Precise translation lookaside buffer error detection and shutdown circuit
A precise TLB error detection and shutdown circuit that detects for two or more matching tag entries in a TLB by providing an array of n units of error detection circuit unit <i>, wherein...
|
|
|
5619673 |
Virtual access cache protection bits handling method and apparatus
A protection update buffer in conjunction with a cache memory that stores data, protection information and data line tags. The protection update buffer also stores cache address tags. By storing...
|
|
|
5619711 |
Method and data processing system for arbitrary precision on numbers
A data processing system 10 comprises an arbitrary precision number C++ class program code 18, which incorporates arbitrary precision arithmetic. The arbitrary precision number program code 18...
|
|
|
5617553 |
Computer system which switches bus protocols and controls the writing of a dirty page bit of an address translation buffer
An electronic computer which uses different bus protocols to transfer information for processor-to-processor communication and for processor-to-peripheral communication. The electronic computer...
|
|
|
5613083 |
Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions
A translation lookaside buffer is described for use with a microprocessor capable of speculative and out-of-order processing of memory instructions. The translation lookaside buffer is non-blocking...
|
|
|
5606683 |
Structure and method for virtual-to-physical address translation in a translation lookaside buffer
A structure and a method are provided in a table lookaside buffer (TLB) for translating a virtual memory address to a physical memory address. The virtual memory address is computed by adding to a...
|
|
|
5604879 |
Single array address translator with segment and page invalidate ability and method of operation
A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the...
|
|
|
5603008 |
Computer system having cache memories with independently validated keys in the TLB
A storage unit for a data processing system includes a cache data buffer, a cache tag, and a translation lookaside buffer (TLB). Storage keys are maintained in the TLB with a separate valid bit,...
|
|
|
5586280 |
Method and apparatus for appending data to compressed records previously stored on a sequentially-accessible storage medium
A method of appending data to compressed data stored on tape (10) in the form of records (CR n ) wherein compressed data is stored in groups (G n ) independently of the record structure of the data...
|
|
|
5586283 |
Method and apparatus for the reduction of tablewalk latencies in a translation look aside buffer
A translation look aside buffer including virtual page table pointer tags provides a system and method for accessing page table entries in page memory of the translation look aside buffer with...
|
|
|
5584003 |
Control systems having an address conversion device for controlling a cache memory and a cache tag memory
A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical...
|
|
|
5581722 |
Memory management unit for managing address operations corresponding to domains using environmental control
A memory management unit (MMU) for controlling a CPU's right to access a memory in order to initiate performance of an operation. The MMU includes a translator for translating a virtual address...
|