Matches 451 - 500 out of 743 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
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5963984 Address translation unit employing programmable page size  
Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside...
5956752 Method and apparatus for accessing a cache using index prediction  
Index prediction is used to access data in a memory array. A virtual address is received at an input. The virtual address is translated to a physical address. The memory array is accessed at a...
5956756 Virtual address to physical address translation of pages with unknown and variable sizes  
A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be...
5956754 Dynamic shared user-mode mapping of shared memory  
A method for use in a multiprocessor computer system where data objects larger than the address space of a single task are mapped in main memory and the translation lookaside buffer (TLB) is...
5953748 Processor with an efficient translation lookaside buffer which uses previous address computation results  
A structure and a method are provided in a table lookaside buffer (TLB) for translating a virtual memory address to a physical memory address. The virtual memory address is computed by adding to a...
5950232 Fetching apparatus for fetching data from a main memory  
A fetching apparatus (20) is for use in a data processing equipment comprising a processor (11) and a main memory (12). The main memory has a page structure comprising a plurality of pages each of...
5946716 Sectored virtual memory management system and translation look-aside buffer (TLB) for the same  
A memory management system is described which divides each virtual page into two or more sectors. Each of these sectors can then be individually loaded into memory in order to reduce bandwidth...
5946715 Page address space with varying page size and boundaries  
A method of addressing a computer subsystem memory comprised of establishing an aperture having a predetermined page size, addressing the memory at address boundaries defining multiples of half the...
5946717 Multi-processor system which provides for translation look-aside buffer address range invalidation and address translation concurrently  
In a multi-processor system, a translation look-aside buffer in a processor can be invalidated without stopping operations of other processors of the multi-processor system. Each processor has a...
5946718 Shadow translation look-aside buffer and method of operation  
For use in an x86-compatible processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for...
5940872 Software and hardware-managed translation lookaside buffer  
A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage...
5937435 System and method for skip-sector mapping in a data recording disk drive  
A data recording disk drive includes a system and method for mapping around skip sectors, both bad sectors and spare sectors. A received logical block address is converted to a corresponding...
5928352 Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry  
Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is...
5930832 Apparatus to guarantee TLB inclusion for store operations  
A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit...
5924126 Method and apparatus for providing address translations for input/output operations in a computer system  
An input circuit for an input/output device adapted for use in a computer system including a first section having a storage circuit holding physical addresses of input/output devices which are...
5924127 Address translation buffer system and method for invalidating address translation buffer, the address translation buffer partitioned into zones according to a computer attribute  
An address translation buffer system in which a searching time of an address translation buffer is shortened. The address translation buffer includes an address translation buffer connected to a...
5918251 Method and apparatus for preloading different default address translation attributes  
A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a...
5918056 Segmentation suspend mode for real-time interrupt support  
A device and method that suspends segmentation addressing and prevents the modification of segmentation information (the segment registers and segment descriptors). By suspending segmentation...
5918250 Method and apparatus for preloading default address translation attributes  
A method and apparatus for installing translations in a translation look-aside buffer. According to the method, each translation contains either a first attribute or a second attribute. Either the...
5914727 Valid flag for disabling allocation of accelerated graphics port memory space  
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer...
5913923 Multiple bus master computer system employing a shared address translation unit  
A multiple bus master computer system employs an interface to a central processor allowing external bus masters to query the central processor with addresses and to receive back translated...
5913222 Color correction method in a virtually addressed and physically indexed cache memory in the event of no cache hit  
In a virtually addressed and physically indexed cache memory, the allocation of a color of a cache entry can be changed for a color allocation of the virtual and physical pages by assigning a color...
5907867 Translation lookaside buffer supporting multiple page sizes  
A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for...
5899994 Flexible translation storage buffers for virtual address translation  
A technique for managing address translation storage buffers (TSBs) supports multiple pools of different TSB sizes and dynamically assigns a process to its own TSB of the proper size as the needs...
5895500 Data processing system with reduced look-up table for a function with non-uniform resolution  
A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive...
5895501 Virtual memory system for vector based computer systems  
A virtual memory management system for a vector based processing system detects early page or segment faults allowing pipelined instructions to be halted and resumed once the pages or segments...
5893931 Lookaside buffer for address translation in a computer system  
A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in...
5890201 Content addressable memory having memory cells storing don't care states for address translation  
A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed....
5875473 Multi-processor system and method for controlling access to a page descriptor during the process of updating the page descriptors  
In a multi-processor system, a page descriptor can be updated in a memory coupled to a processor without stopping operations of other processors. Each processor has a page descriptor comparator...
5873129 Method and apparatus for extending physical system addressable memory  
The extension of the physical addressable memory space of a computer system is achieved by a secondary storage subsystem controller which intercepts requests to non-existent physical random access...
5873126 Memory array based data reorganizer  
Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively...
5873123 Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries  
A processor and method for translating a nonphysical address into a physical address are disclosed. A determination is made if a first entry set which could contain a particular entry that...
5870599 Computer system employing streaming buffer for instruction preetching  
Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for M physical streaming buffer...
5864876 DMA device with local page table  
A DMA device which can quickly access main memory over a system bus without requiring an allocation of a contiguous block of memory on start-up. This is accomplished by providing a copy of the host...
5860147 Method and apparatus for replacement of entries in a translation look-aside buffer  
Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is...
5860141 Method and apparatus for enabling physical memory larger than corresponding virtual memory  
A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length,...
5860146 Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces  
A computer system includes a data processor, a primary translation lookaside buffer for storing page table entries and translating virtual addresses into physical addresses, local memory coupled to...
5860145 Address translation device storage last address translation in register separate from TLB  
The address translation device includes a virtual page number register for storing a last-accessed virtual page number, a physical page number register for storing a physical page number...
5854913 Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures  
A microprocessor which supports two distinct instruction-set architectures. The microprocessor includes a mode control unit which enables extensions and/or limitations to each of the two...
5852738 Method and apparatus for dynamically controlling address space allocation  
A method for managing a memory address space in a memory system, the memory system having multiple block address translation entries, each entry defining a portion of the memory address space,...
5835964 Virtual memory system with hardware TLB and unmapped software TLB updated from mapped task address maps using unmapped kernel address map  
A virtual memory system includes a hardware-implemented translation lookaside buffer (HTLB) as well as a software-implemented translation lookaside buffer (VTLB). The VTLB is in the system's...
5835963 Processor with an addressable address translation buffer operative in associative and non-associative modes  
A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the...
5835928 Circuitry and method for relating first and second memory locations where the second memory location stores information from the first memory location  
A first group of memory locations stores information. The first group is arranged into multiple congruence classes of memory locations. The congruence classes include a first congruence class...
5822785 Data transfer using local and global address translation and authorization  
A system information storage section stores access information showing attributes for accessing a storage peculiar to a processor and storages peculiar to other processors by relating the access...
5819079 Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch  
A computer system includes an instruction prefetching mechanism that detects whether an instruction to be prefetched is located in a region of memory that is uncacheable. To perform an instruction...
5809562 Cache array select logic allowing cache array size to differ from physical page size  
An apparatus and method for organizing a data array within a cache system to store a plurality of physical pages of data. A single data array is associated with a plurality of tag arrays, each tag...
5809563 Method and apparatus utilizing a region based page table walk bit  
A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookaside buffer (TLB) is...
5802568 Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers  
A simplified or pseudo least-recently-used (LRU) process and circuit in a cache memory or translation lookaside table (TLB) maintains status bits to identify which entries are valid and which...
5784706 Virtual to logical to physical address translation for distributed memory massively parallel processing systems  
Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a...
5784708 Translation mechanism for input/output addresses  
A computing system includes a memory bus, an input/output bus, a main memory, and an input/output adapter. The memory bus provides information transfer. The input/output bus also provides...
Matches 451 - 500 out of 743 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >