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7404064 Method and device for calculating addresses of a segmented program memory  
A method and a device for converting a virtual address of a program executed by a processor and provided by a program counter into a physical address in a program memory, the program having been...
7403974 True zero-copy system and method  
A method and system for moving data from a network layer into a physical memory page, wherein said physical memory page comprising a plurality of physical memory clusters, creating a logical page...
7398362 Programmable interleaving in multiple-bank memories  
A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank...
7395405 Method and apparatus for supporting address translation in a virtual machine environment  
In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which...
7395397 Electronic apparatus with page table management of program, data processing method and computer program  
An electronic apparatus executes a program by using a page table for managing, on a page unit basis, virtual and physical addresses of the program recorded in a first recording medium. The page...
7395278 Transaction consistent copy-on-write database  
A database view of a database is created which provides a transaction-consistent view of an existing database at a previous time. Each database view contains all the information needed to, along...
7389402 Microprocessor including a configurable translation lookaside buffer  
A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address...
7389400 Apparatus and method for selectively invalidating entries in an address translation cache  
An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each...
7386700 Virtual-to-physical address translation in a flash file system  
A flash memory management system for a memory for accessing data from a host, the system including physical units and virtual units of the memory and a mapping mechanism of each virtual unit into...
7383415 Hardware demapping of TLBs shared by multiple threads  
In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one...
7383414 Method and apparatus for memory-mapped input/output  
A method of managing memory mapped input/output (I/O) for a run-time environment is disclosed, in which opaque references are used for accessing information blocks included in files used in a...
7383391 Prefetch mechanism based on page table attributes  
A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated...
7380098 Method and system for caching attribute data for matching attributes with physical addresses  
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
7380037 Data transmitter between external device and working memory  
A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU...
7376808 Method and system for predicting the performance benefits of mapping subsets of application data to multiple page sizes  
A method for modeling the performance of memory address translation mechanism (MATM), comprises: a) receiving an execution profile that contains a memory address reference stream of an application,...
7376782 Index/data register pair for indirect register access  
A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are...
7373479 Method to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table  
A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching....
7373477 Fragmentation executing method and storage device  
When a host apparatus transfers/swaps stored information between user sectors in a storage device for the purpose of defragmentation or the like, the storage device is allowed to perform the data...
7370174 Method, system, and program for addressing pages of memory by an I/O device  
Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical...
7370160 Virtualizing memory type  
A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization...
7370137 Inter-domain data mover for a memory-to-memory copy engine  
Address translation for a source and destination of the data that utilizes different page tables. A direct memory access (DMA) engine is used as a memory-to-memory copy engine by utilizing a...
7366829 TLB tag parity checking without CAM read  
An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need...
7363491 Resource management in security enhanced processors  
A processor divides resources into secure resources and non-secure resources. Virtual-to-physical address translation page tables may be stored in either secure or non-secure memory.
7363463 Method and system for caching address translations from multiple address spaces in virtual machines  
A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged...
7363462 Performing virtual to global address translation in processing subsystem  
A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. Each active device in one of the plurality of nodes includes a...
7360056 Multi-node system in which global address generated by processing subsystem includes global to local translation information  
A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory...
7360054 Method and apparatus for direct conveyance of physical addresses from user level code to peripheral devices in virtual memory systems  
A memory system and a set of user-level instructions that are callable from user-level code for converting virtual addresses to physical addresses and conveying the physical addresses to peripheral...
7356667 Method and apparatus for performing address translation in a computer system  
An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry...
7353361 Page replacement policy for systems having multiple page sizes  
In a data processing system utilizing multiple page sizes for virtual memory paging, a system, method, and article of manufacture for managing page replacement. In one embodiment, the page...
7353360 Method for maximizing page locality  
A method for maximizing page locality within a networking system operationally attached to a plurality of processing entities wherein each processing entity either shares or includes a...
7350028 Use of a translation cacheable flag for physical address translation and memory protection in a host  
A host coupled to a switched fabric including one or more fabric-attached I/O controllers. Such a host may comprise a processor; a host memory coupled to the processor; and a host-fabric adapter...
7350017 Magnetic disk unit, file management system, and file management method  
A file management system including a hard disk unit and a file management unit. The file management unit manages data to be read and written from and into the hard disk unit such that data in a...
7346755 Memory quality assurance  
An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations....
7340486 System and method for file system snapshot of a virtual logical disk  
A system and method generates a consistent file system snapshot of a virtual logical disk (VLD). The system and method ensures that database files are stored on the VLD are consistent at the time a...
7337299 Storage apparatus having virtual-to-actual device addressing scheme  
A technique is provided in which, even when the number of devices and device addresses handled in the storage apparatus side increases, it is possible to access all the devices and save used...
7337296 Managing physical memory in a virtual memory computer  
A method for use in a computer. A user of the computer stores a table of selections in a permanent memory structure of the computer, each selection indicating a memory object and one of at least...
7334109 Method and apparatus for improving segmented memory addressing  
A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.
7334108 Multi-client virtual address translation system with translation units of variable-range size  
A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that...
7330959 Use of MTRR and page attribute table to support multiple byte order formats in a computer system  
Computer technology supports multiple byte order formats, separately or simultaneously. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order...
7330942 Method for efficient virtualization of physical memory in a virtual-machine monitor  
Various embodiments of the present invention are directed to efficient provision, by a virtual-machine monitor, of a virtual, physical memory interface to guest operating systems and other programs...
7325093 Reproducing method, reproducing apparatus, recording method, recording apparatus, and method for generating a management table  
A recording method includes the steps of reading a management table for managing whether data are recorded on a recording medium in units of a first recording segment; detecting whether the first...
7325059 Bounded index extensible hash-based IPv6 address lookup method  
The present invention provides a technique for efficiently looking up address-routing information in an intermediate network node, such as a router. To that end, the node locates routing...
7310721 Shadow page tables for address translation control  
In a computer system that employs virtual memory, multiple versions of a given page are stored: a directory version, a table version, and a data version. The data version contains the data that a...
7299337 Enhanced shadow page table algorithms  
Enhanced shadow page table algorithms are presented for enhancing typical page table algorithms. In a virtual machine environment, where an operating system may be running within a partition, the...
7299336 Scaling address space utilization in a multi-threaded, multi-processor computer  
Scaling address space utilization in a multi-threaded, multi-processor computer, including attaching to process memory of an exporting process a region of virtual memory specified in a cross-memory...
7299335 Translation information retrieval transparent to processor core  
A system for obtaining translation information from a data processing system transparent to the operation of a processor core of the data processing system. In one embodiment, the processor...
7299328 Method and apparatus for disc drive data security using a defect list  
Method and apparatus for storing and retrieving copy-protected data within storage devices such as, for example, disc drives. Data that is to be copy protected is written on the storage device. A...
7296139 In-memory table structure for virtual address translation system with translation units of variable range size  
A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that...
7296138 Method and apparatus to hook shared libraries across all processes on windows  
A process page table entry (PTE) associated with a process is located, and a determination is made whether the process PTE is prototype PTE. If the process PTE is a prototype PTE, the location of...
7296137 Memory management circuitry translation information retrieval during debugging  
A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines...
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