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8838915 Cache collaboration in tiled processor systems  
The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a...
8838937 Methods, systems and computer readable medium for writing and reading data  
A flash memory controller, a computer readable medium and a method for writing to a flash memory device, the method may include receiving multiple logical pages, each logical page having a logical...
8838935 Apparatus, method, and system for implementing micro page tables  
In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also...
8838875 Systems, methods and computer program products for operating a data processing system in which a file delete command is sent to an external storage device for invalidating data thereon  
A data processing system that includes a host system and an external data storage device with an erase before write memory device thereon can be operated by sending a file delete command from the...
8838922 Computer system, server module, and storage module  
An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a...
8838933 Data communications in a parallel active messaging interface of a parallel computer  
Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a t...
8832415 Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests  
A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second...
8832383 Delayed replacement of TLB entries  
A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry...
8825945 Mapping different portions of data to different pages of multi-level non-volatile memory  
The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level...
8825984 Address translation mechanism for shared memory based inter-domain communication  
A technique for “zero copy” transitive communication of data between virtual address domains maintains a translation table hierarchy for each domain. The hierarchy of each domain includes a por...
8825983 Data communications in a parallel active messaging interface of a parallel computer  
Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a t...
8819391 Memory controller with enhanced block management techniques  
Methods and apparatuses for managing unusable blocks in a memory module are provided. The memory table may include a plurality of unusable block addresses in the memory module where the plurality...
8819385 Device and method for managing a flash memory  
A method for accessing a flash memory, the method includes: receiving a read request that is associated with a logical address that is mapped to a physical address of a set of flash memory cells;...
8819392 Providing metadata in a translation lookaside buffer (TLB)  
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA)...
8819388 Control of on-die system fabric blocks  
Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a...
8819359 Hybrid interleaving in memory modules by interleaving physical addresses for a page across ranks in a memory module  
A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses...
8817621 Network virtualization apparatus  
Some embodiments provide a network virtualization apparatus for managing a plurality of managed switching elements that forward data in a network. The network virtualization apparatus comprises a...
8819372 Preventing data loss during reboot and logical storage resource management device  
According to an example, in a method for preventing data loss during reboot, a logical storage resource management device may pre-allocate reserved memory for storing a storage resource mapping...
8819329 Nonvolatile storage device, access device and nonvolatile storage system  
A memory controller includes a reading/writing control unit for controlling writing and reading of data to and from a physical block of a nonvolatile memory, a writing mode table for storing one of...
8819389 Administering registered virtual addresses in a hybrid computing environment including maintaining a watch list of currently registered virtual addresses by an operating system  
Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host...
8817620 Network virtualization apparatus and method  
Some embodiments provide a network virtualizer for managing several managed switching elements that forward data in a network. The virtualizer includes an interface for receiving input logical...
8799620 Linear to physical address translation with support for page attributes  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system...
8799621 Translation table control  
Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a...
8798085 Techniques to process network protocol units  
Techniques are described herein that can be used to process inbound network protocol units. In some implementations, the techniques may process inbound DDP segments. In some implementations, a...
8793467 Variable length encoding in a storage system  
A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries...
8793468 Translation map simplification  
A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining...
8793428 System and method to reduce trace faults in software MMU virtualization  
A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained...
8788788 Logical sector mapping in a flash storage array  
A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem...
8788754 Virtualized storage system and method of operating thereof  
A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage...
8782338 Method for wear leveling in a nonvolatile memory  
A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing...
8775153 Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment  
In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation...
8775752 Virtual memory management apparatus and memory management apparatus  
A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a...
8769242 Translation map simplification  
A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining...
8769184 System and method to prioritize large memory page allocation in virtualized systems  
The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is...
8769356 Bad page management in memory device or system  
A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided...
8769192 Data read method for a plurality of host read commands, and flash memory controller and storage system using the same  
A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related...
8762127 Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment  
In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation...
8762683 Device and method for memory addressing  
An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the...
8762684 Hardware assistance for page table coherence with guest page mappings  
Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to...
8762682 Data storage apparatus providing host full duplex operations using half duplex storage devices  
A data storage apparatus includes a command processor that receives write commands and data blocks from a host, the write commands comprising block ID's (BID) corresponding to data blocks; storage...
8756383 Random cache line selection in virtualization systems  
A mechanism for random cache line selection in virtualization systems is disclosed. A method includes maintaining a secondary data structure representing a plurality of memory pages, the secondary...
8756401 Method for controlling non-volatile semiconductor memory system  
In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply...
8756373 Virtualized data storage in a network computing environment  
Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module...
8756361 Disk drive modifying metadata cached in a circular buffer when a write operation is aborted  
A disk drive is disclosed comprising a head actuated over a rotatable disk. A write operation is processed to write data on the disk using the head, wherein prior to writing the data on the disk,...
8750119 Network control apparatus and method with table mapping engine  
Some embodiments provide a controller for managing a plurality of managed switching elements that forward data through a network. The controller comprising a first set of tables for storing input...
8745307 Multiple page size segment encoding  
An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of...
8745349 Consolidating control areas  
A detection module selects logically adjacent first and second control areas of a cluster. The detection module further determines that the first and second control areas satisfy a migration test...
8738889 Generating multiple address space identifiers per virtual machine to switch between protected micro-contexts  
Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes...
8738890 Coupled symbiotic operating system  
A single application can be executed across multiple execution environments in an efficient manner if at least a relevant portion of the virtual memory assigned to the application was equally...
8738851 Device and memory system for swappable memory  
An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit...