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8868882 Storage architecture for backup application  
Aspects of the subject matter described herein relate to a storage architecture. In aspects, an address provided by a data source is translated into a logical storage address of virtual storage....
8868822 Data-processing method, program, and system  
A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and...
8868865 Computer system, server module, and storage module  
An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a...
8868883 Virtual memory management for real-time embedded devices  
An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write...
8862813 Method, computer program product and appartus for accelerating responses to requests for transactions involving data operations  
Responding to IO requests made by an application to an operating system within a computing device implements IO performance acceleration that interfaces with the logical and physical disk...
8862858 Method and system for fast block storage recovery  
A computer-implemented method and apparatus manages block mapping. The block mapping maps physical blocks in a block storage device to virtual blocks of a virtual address space. The method involves...
8862857 Data access processing method and apparatus  
A data access processing method and apparatus, the method comprising: copying a kernel code and a global descriptor table on a memory of each of nodes respectively (101); making base addresses of...
8862854 Configurable decoder with applications in FPGAs  
The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output...
8862860 Flash storage partial page caching  
Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks...
8856438 Disk drive with reduced-size translation table  
A disk drive is disclosed that utilizes an additional address mapping layer between logical addresses used by a host system and physical locations in the disk drive. Physical locations configured...
8856489 Logical sector mapping in a flash storage array  
A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem...
8850158 Apparatus for processing remote page fault and method thereof  
Disclosed is an apparatus for processing a remote page fault included in an optional local node within a cluster system configuring a large integration memory (CVM) by integrating individual...
8850101 System and method to reduce memory access latencies using selective replication across multiple memory ports  
In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system...
8850154 Processing system having memory partitioning  
Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition....
8842472 Partial block erase architecture for flash memory  
A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into...
8843727 Performance enhancement of address translation using translation tables covering large address spaces  
An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset...
8838915 Cache collaboration in tiled processor systems  
The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a...
8838937 Methods, systems and computer readable medium for writing and reading data  
A flash memory controller, a computer readable medium and a method for writing to a flash memory device, the method may include receiving multiple logical pages, each logical page having a logical...
8838935 Apparatus, method, and system for implementing micro page tables  
In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also...
8838875 Systems, methods and computer program products for operating a data processing system in which a file delete command is sent to an external storage device for invalidating data thereon  
A data processing system that includes a host system and an external data storage device with an erase before write memory device thereon can be operated by sending a file delete command from the...
8838922 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Computer system, server module, and storage module
 
An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a...
8838933 Data communications in a parallel active messaging interface of a parallel computer  
Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a t...
8832415 Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests  
A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second...
8832383 Delayed replacement of TLB entries  
A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry...
8825945 Mapping different portions of data to different pages of multi-level non-volatile memory  
The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level...
8825984 Address translation mechanism for shared memory based inter-domain communication  
A technique for “zero copy” transitive communication of data between virtual address domains maintains a translation table hierarchy for each domain. The hierarchy of each domain includes a por...
8825983 Data communications in a parallel active messaging interface of a parallel computer  
Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a t...
8819391 Memory controller with enhanced block management techniques  
Methods and apparatuses for managing unusable blocks in a memory module are provided. The memory table may include a plurality of unusable block addresses in the memory module where the plurality...
8819385 Device and method for managing a flash memory  
A method for accessing a flash memory, the method includes: receiving a read request that is associated with a logical address that is mapped to a physical address of a set of flash memory cells;...
8819392 Providing metadata in a translation lookaside buffer (TLB)  
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA)...
8819388 Control of on-die system fabric blocks  
Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a...
8819359 Hybrid interleaving in memory modules by interleaving physical addresses for a page across ranks in a memory module  
A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses...
8817621 Network virtualization apparatus  
Some embodiments provide a network virtualization apparatus for managing a plurality of managed switching elements that forward data in a network. The network virtualization apparatus comprises a...
8819372 Preventing data loss during reboot and logical storage resource management device  
According to an example, in a method for preventing data loss during reboot, a logical storage resource management device may pre-allocate reserved memory for storing a storage resource mapping...
8819329 Nonvolatile storage device, access device and nonvolatile storage system  
A memory controller includes a reading/writing control unit for controlling writing and reading of data to and from a physical block of a nonvolatile memory, a writing mode table for storing one of...
8819389 Administering registered virtual addresses in a hybrid computing environment including maintaining a watch list of currently registered virtual addresses by an operating system  
Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host...
8817620 Network virtualization apparatus and method  
Some embodiments provide a network virtualizer for managing several managed switching elements that forward data in a network. The virtualizer includes an interface for receiving input logical...
8799620 Linear to physical address translation with support for page attributes  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system...
8799621 Translation table control  
Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a...
8798085 Techniques to process network protocol units  
Techniques are described herein that can be used to process inbound network protocol units. In some implementations, the techniques may process inbound DDP segments. In some implementations, a...
8793467 Variable length encoding in a storage system  
A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries...
8793468 Translation map simplification  
A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining...
8793428 System and method to reduce trace faults in software MMU virtualization  
A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained...
8788788 Logical sector mapping in a flash storage array  
A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem...
8788754 Virtualized storage system and method of operating thereof  
A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage...
8782338 Method for wear leveling in a nonvolatile memory  
A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing...
8775153 Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment  
In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation...
8775752 Virtual memory management apparatus and memory management apparatus  
A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a...
8769242 Translation map simplification  
A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining...
8769184 System and method to prioritize large memory page allocation in virtualized systems  
The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is...