|
Match
|
Document |
Document Title |
|
|
7620769 |
Recycling partially-stale flash blocks using a sliding window for multi-level-cell (MLC) flash memory
A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined...
|
|
|
7620766 |
Transparent sharing of memory pages using content comparison
A computer system has one or more software contexts that share use of a memory that is divided into units such as pages. In the preferred embodiment of the invention, the contexts are, or include,...
|
|
|
7617381 |
Demand paging apparatus and method for embedded system
A demand paging apparatus and a method for an embedded system are provided. The demand paging apparatus includes a nonvolatile storage device, a physical memory, a demand paging window, and a...
|
|
|
7617380 |
System and method for synchronizing translation lookaside buffer access in a multithread processor
A system and method for synchronizing translation lookaside buffer (TLB) access in a multithread processor is disclosed. When a first exception is found while searching the TLB, the exception is...
|
|
|
7617377 |
Splitting endpoint address translation cache management responsibilities between a device driver and device driver services
Mechanisms for splitting responsibilities for communicating with an endpoint between a device driver and device driver services are provided. With these mechanisms, the device driver is responsible...
|
|
|
7617376 |
Method and apparatus for accessing a memory
The disclosed embodiments relate to an optimized memory registration mechanism that may comprise an upper layer protocol that associates I/O buffers with memory regions and that manages steering...
|
|
|
7613898 |
Virtualizing an IOMMU
In one embodiment, a system comprises one or more input/output (I/O) devices; an I/O memory management unit (IOMMU) coupled to receive memory requests sourced by the I/O devices and configured to...
|
|
|
7606994 |
Cache memory system including a partially hashed index
In one embodiment, a cache memory system includes a cache memory coupled to a cache controller. The cache memory controller may receive an address and generate an index value corresponding to the...
|
|
|
7603530 |
Methods and structure for dynamic multiple indirections in a dynamically mapped mass storage device
Methods and structures for dynamic multiple indirections to improve reliability and performance of a dynamically mapped storage devices. In a dynamically mapped storage device in which all user...
|
|
|
7599951 |
Continuous data backup
Handling writing new data includes creating a journal entry that points to a first storage location containing old data to be replaced by the new data, where the journal entry is maintained after...
|
|
|
7596677 |
Paging cache optimization for virtual machine
A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for...
|
|
|
7596663 |
Identifying a cache way of a cache access request using information from the microtag and from the micro TLB
A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor;...
|
|
|
7596655 |
Flash storage system with data storage security
A flash storage comprises a flash memory, including a plurality of physical memory blocks, each of physical memory blocks comprising a plurality of memory segments, and a plurality of physical...
|
|
|
7594094 |
Move data facility with optional specifications
A move data facility is provided that enables optional specifications to be indicated to flexibly control the move operation. Data may be moved from any address space to any other address space...
|
|
|
7594064 |
Free sector manager for data stored in flash memory devices
A flash driver tracks data stored in a flash memory device through the use of logical-to-physical sector mapping. The mapping is stored in a data structure and allows data to be written into the...
|
|
|
7590817 |
Communicating with an I/O device using a queue data structure and pre-translated addresses
Mechanisms for communicating with an I/O device or endpoint using a queue data structure and pre-translated addresses associated with the queue data structure are provided. With the mechanisms, a...
|
|
|
7587575 |
Communicating with a memory registration enabled adapter using cached address translations
Mechanisms for communicating with a memory registration enabled adapter, such as an InfiniBand™ host channel adapter, are provided. With the mechanisms, device driver services may be invoked by a...
|
|
|
7587574 |
Address translation information storing apparatus and address translation information storing method
Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.
|
|
|
7577817 |
Storage virtualization system and methods
Storage virtualization systems and methods that allow customers to manage storage as a utility rather than as islands of storage which are independent of each other. A demand mapped virtual disk...
|
|
|
7577816 |
Remote translation mechanism for a multinode system
The present invention provides a method of initializing shared memory in a multinode system. The method includes building a local address space in each of a plurality of nodes and exporting the...
|
|
|
7577764 |
Method, system, and computer program product for virtual adapter destruction on a physical adapter that supports virtual adapters
A method, computer program product, and distributed data processing system for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter...
|
|
|
7577707 |
Method, system, and program for executing data transfer requests
Provided are a method, system, and program for transferring data between an initiator node and target node. A request is received conforming to a first data transfer protocol at the initiator node...
|
|
|
7574464 |
System and method for enabling a storage system to support multiple volume formats simultaneously
A system and method enables a storage system to support multiple volume type simultaneously. A volume type field is contained within a file system information block that permits the storage system...
|
|
|
7573484 |
Image processing apparatus and controlling method therefor
An image processing apparatus for managing a memory device having a plurality of storage areas including a storage area storing out-of-use information and a free area storing no information, the...
|
|
|
7562204 |
Identifying and relocating relocatable kernel memory allocations in kernel non-relocatable memory
A method for identifying relocatable kernel memory allocations in kernel non-relocatable memory is described. In this method, a physical address hardware mapping entry (PA HME) for each process...
|
|
|
7558940 |
Virtual memory translator for real-time operating systems
A multi-tiered lookup table is used to progressively map a virtual address to a specific control word that facilitates resolution of the virtual address for a translation lookaside buffer (TLB)...
|
|
|
7558939 |
Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory...
|
|
|
7555628 |
Synchronizing a translation lookaside buffer to an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
|
|
|
7555605 |
Data processing system having cache memory debugging support and method therefor
A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus....
|
|
|
7555591 |
Method and system of memory management
The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to the processor. The processor is...
|
|
|
7552319 |
Methods and apparatus to manage memory access
An example method involves detecting a memory relocation process and disabling memory access to a memory block in response to detecting the memory relocation process. The example method also...
|
|
|
7552277 |
Distributed buffer integrated cache memory organization and method for reducing energy consumption thereof
A cache memory that may include a content addressable memory, random access memory (CAMRAM) cache and method for managing a cache to reduce cache energy consumption. A cache buffer receives...
|
|
|
7552275 |
Method of performing table lookup operation with table index that exceeds CAM key size
In a packet switching device or system, such as a router, switch, combination router/switch, or component thereof, a method of and system for performing a table lookup operation using a lookup...
|
|
|
7552255 |
Dynamically partitioning pipeline resources
In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing...
|
|
|
7552254 |
Associating address space identifiers with active contexts
In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space...
|
|
|
7549036 |
Management of access to data from memory
Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command...
|
|
|
7549012 |
Memory device with sector pointer structure
A pointer structure on the storage unit of a non-volatile memory maintains a correspondence between the physical and logical address. The controller and storage unit transfer data on the basis of...
|
|
|
7548999 |
Chained hybrid input/output memory management unit
In one embodiment, an input/output (I/O) node comprises an I/O memory management unit (IOMMU) configured to translate memory requests. The I/O node is configured to couple to an interconnect and to...
|
|
|
7546631 |
Embedded management system for a physical device having virtual elements
A single management facility in a virtualized system that facilitates the presentation of either a virtual element view or system view to a network management user depending upon the user's access...
|
|
|
7546440 |
Non-volatile memory devices and control and operation thereof
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase...
|
|
|
7543132 |
Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data...
|
|
|
7543131 |
Controlling an I/O MMU
In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an...
|
|
|
7543084 |
Method for destroying virtual resources in a logically partitioned data processing system
A method for directly destroying one or more virtual resources that reside within a physical adapter and that are associated with a virtual host. Specifically, the present invention is directed to...
|
|
|
7536531 |
Scaling address space utilization in a multi-threaded, multi-processor computer
Scaling address space utilization in a multi-threaded, multi-processor computer, including attaching to process memory of an exporting process a region of virtual memory specified in a cross-memory...
|
|
|
7536530 |
Method and apparatus for determining a dynamic random access memory page management implementation
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the...
|
|
|
7533220 |
Microprocessor with improved data stream prefetching
A microprocessor coupled to a system memory has a memory subsystem with a translation look-aside buffer (TLB) for storing TLB information. The microprocessor also includes an instruction decode...
|
|
|
7530067 |
Filtering processor requests based on identifiers
Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the...
|
|
|
7529906 |
Sharing memory within an application using scalable hardware resources
Systems and methods include translating a virtual memory address into a physical memory address in a multi-node system that is initiated by providing the virtual memory address at a source node. A...
|
|
|
7529799 |
Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
|
|
|
7526627 |
Storage system and storage system construction control method
In the present invention, memory resources are effectively utilized by virtualizing external memory resources as internal memory resources, and erroneous operations that destroy the cooperative...
|