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7299328 Method and apparatus for disc drive data security using a defect list  
Method and apparatus for storing and retrieving copy-protected data within storage devices such as, for example, disc drives. Data that is to be copy protected is written on the storage device. A...
7296139 In-memory table structure for virtual address translation system with translation units of variable range size  
A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that...
7296138 Method and apparatus to hook shared libraries across all processes on windows  
A process page table entry (PTE) associated with a process is located, and a determination is made whether the process PTE is prototype PTE. If the process PTE is a prototype PTE, the location of...
7296137 Memory management circuitry translation information retrieval during debugging  
A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines...
7296136 Methods and systems for loading data from memory  
According to an exemplary embodiment of the present invention, a method for loading data from at least one memory device includes the steps of loading a first value from a first memory location of...
7293157 Logically partitioning different classes of TLB entries within a single caching structure  
One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving...
7293156 Distributed independent cache memory  
A system for transferring data to and from one or more slow-access-time-mass-storage nodes which store data at respective first ranges of logical block addresses (LBAs), including a plurality of...
7293155 Management of access to data from memory  
Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command...
7290102 Point in time storage copy  
A storage system permits virtual storage of user data by implementing a logical disk mapping structure that provides access to user data stored on physical storage media and methods for generating...
7287124 Lazy flushing of translation lookaside buffers  
Address translation control (ATC) limits the mappings between virtual and physical addresses in order to implement a memory access policy. Each processor in a multi-processor system maintains a...
7287101 Direct memory access using memory descriptor list  
Machine-readable media, methods, and apparatus are described for transferring data. In some embodiments, an operating system may allocate pages to a buffer and may build a memory descriptor list...
7284112 Multiple page size address translation incorporating page size prediction  
Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation...
7284100 Invalidating storage, clearing buffer entries, and an instruction therefor  
Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure...
7281115 Method, system and program product for clearing selected storage translation buffer entries  
An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of...
7280536 Fast path for performing data operations  
Described are techniques used in a computer system for handling data operations to storage devices. A switching fabric includes one or more fast paths for handling lightweight, common data...
7278008 Virtual address translation system with caching of variable-range translation clusters  
A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that...
7275143 System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses  
A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an...
7275064 Apparatus for managing virtualized-information  
A virtualized-information management apparatus for managing corresponding information between real storage areas of a plurality of storages connected to a network and a virtual storage-area built...
7272699 Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs  
A method, a computer program, and an apparatus are provided for flexible SC to SR mapping to enable sub-page activation in an XDR™ memory system. An XDR™ memory system may allow system page...
7269825 Method and system for relative address translation  
A method and system to provide improved operation of a software emulated platform through the use of a relative address translation cache containing a plurality of cache sets. Each address...
7269710 Program memory space expansion for particular processor instructions  
A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2 N memory locations in a regular portion...
7266651 Method for in-place memory interleaving and de-interleaving  
A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR...
7263593 Virtualization controller and data transfer control method  
Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a...
7260669 Semiconductor integrated circuits  
When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus...
7257694 Method for allocating storage area to virtual volume  
In a system where a storage device is coupled to a computer, a storage area in the storage device is efficiently allocated to the computer. The system comprises a virtualization apparatus to be...
7257643 Method and apparatus to improve network routing  
A method and apparatus to route information in a network is described. A technique is described to search for routine information that uses a first technique on at least a portion of a first value...
7249241 Method and apparatus for direct virtual memory address caching  
A system including a direct virtual memory access engine configured to request that data is stored in a memory, wherein a request for the data includes a I/O virtual address, a mapping table...
7249204 Data transfer control device electronic equipment and method data transfer control  
A data transfer control device and electronic equipment that make it possible to implement high-speed data transfer while observing restriction that prevent the traversing of page boundaries. A...
7246208 Storage subsystem and storage subsystem control method  
The present invention partitions a cache region of a storage subsystem for each user and prevents interference between user-dedicated regions. A plurality of CLPR can be established within the...
7243208 Data processor and IP module for data processor  
In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P 0 ), which is subjected to the address...
7236987 Systems and methods for providing a storage virtualization environment  
A storage virtualization environment is provided that includes a system for providing one or more virtual volumes. The system may include a host system and a set of storage devices, each of which...
7234037 Memory mapped Input/Output operations  
A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate...
7231502 Method and system for storing data  
Data is stored by utilizing a first operating mode and a second operating mode. In one embodiment, in the first operating mode, a continuous replication method is utilized to store data on a...
7225317 System and method for managing storage networks and for managing scalability of volumes in such a network  
This invention is a system and method for managing one or more data storage networks using a new architecture. A method for handling logical to physical mapping is included in one embodiment with...
7216199 Disk control system and method  
In a disk control system having a RAID controller for continuously writing data on a data stripe composed of a plurality disk apparatus, in response to a write request, data blocks are sequentially...
7209794 Controller with interface attachment  
A controller with attachments for controlling specific electronic circuits is disclosed. Each attachment has a connector connectable to the electronic circuit to be controlled, and a memory...
7203792 Method for balancing wear when writing data in a flash memory  
A method for modifying file contents of a flash file stored in a flash memory while balancing wear of the flash memory includes: finding first file nodes recording the file contents to be modified;...
7200840 Method and apparatus for enabling access to global data by a plurality of codes in an integrated executable for a heterogeneous architecture  
In the present invention, global information is passed from a first execution environment to a second execution environment, wherein both the first and second processor units comprise separate...
7200734 Operating-system-transparent distributed memory  
Various embodiments of the present invention provide distributed computing systems featuring an operating-system-transparent distributed memory that, among other things, facilitates...
7197620 Sparse matrix paging system  
A sparse matrix paging system is provided that dynamically allocates memory resources on demand. In some cases, this is accomplished by dynamically allocating memory resources, preferably only...
7197601 Method, system and program product for invalidating a range of selected storage translation table entries  
Selected units of storage, such as segments of storage or regions of storage, may be invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure...
7197595 Nonvolatile memory and method of address management  
A nonvolatile memory has plural memory blocks, each having a plurality of sub memory blocks, and is capable of programming to a first sub memory block within a first memory block and a second sub...
7191306 Flash memory, and flash memory access method and apparatus  
A flash memory, and a flash memory access method and apparatus allowing memory access and error block recovery by creating a mapping table representing a physical address and status of a data block...
7188229 Method and apparatus for memory management in a multi-processor computer system  
Improved techniques and systems for accommodating TLB shootdown events in multi-processor computer systems are disclosed. A memory management unit (MMU) having a TLB miss handler and miss exception...
7185172 CAM-based search engine devices having index translation capability  
An integrated circuit chip includes a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine....
7185171 Semiconductor integrated circuit  
There is provided a semiconductor integrated circuit which assures sufficiently lower power consumption of a translation look-aside buffer without deterioration of operation rate performance...
7185169 Virtual physical drives  
A system includes a processor, a storage system having one or more physical storage devices, and a controller coupled to the processor and the storage system. The controller maintains a virtual...
7185020 Generating one or more block addresses based on an identifier of a hierarchical data structure  
A storage system includes a storage medium containing blocks identified by block addresses. The storage medium stores hierarchical data structures, each hierarchical data structure containing...
7181590 Method for page sharing in a processor with multiple threads and pre-validated caches  
A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded...
7181589 System and method for performing address translation in a computer system  
An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address...
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