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7590830 |
Method and structure for concurrent branch prediction in a processor
Concurrently branch predicting for multiple branch-type instructions demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the...
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7584328 |
Method, apparatus, and a system for efficient context switch
A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per...
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7562192 |
Microprocessor, apparatus and method for selective prefetch retire
An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system...
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7558922 |
Apparatus and method for quick retrieval of search data by pre-feteching actual data corresponding to search candidate into cache memory
A storage system includes a client host, a storage device, and a separate data search appliance. The client software executing on the client host composes a query and sends a data search request to...
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7543132 |
Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data...
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7536530 |
Method and apparatus for determining a dynamic random access memory page management implementation
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the...
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7533220 |
Microprocessor with improved data stream prefetching
A microprocessor coupled to a system memory has a memory subsystem with a translation look-aside buffer (TLB) for storing TLB information. The microprocessor also includes an instruction decode...
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7529891 |
Balanced prefetching exploiting structured data
Balanced prefetching automatically balances the benefits of prefetching data that has not been accessed recently against the benefits of caching recently accessed data, and can be applied to most...
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7519777 |
Methods, systems and computer program products for concomitant pair prefetching
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
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7516278 |
System controller, speculative fetching method, and information processing apparatus
A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache,...
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7512699 |
Managing position independent code using a software framework
A method for managing position independent code using a software framework is presented. A software framework provides the ability to cache multiple plug-in's which are loaded in a processor's...
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7509472 |
Collapsible front-end translation for instruction fetch
Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases...
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7500061 |
Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program
A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to...
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7493621 |
Context switch data prefetching in multithreaded computer
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
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7493451 |
Prefetch unit
In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each...
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7493450 |
Method of triggering read cache pre-fetch to increase host read throughput
Exemplary systems and methods include pre-fetching data in response to a read cache hit. Various exemplary methods include priming a read cache with initial data, and triggering a read pre-fetch...
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7478197 |
Adaptive mechanisms for supplying volatile data copies in multiprocessor systems
In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later...
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7454590 |
Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores
In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises...
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7434004 |
Prefetch prediction
Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution...
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7426625 |
Data processing system and computer program product for support of system memory addresses with holes
A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating...
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7421694 |
Systems and methods for enhancing performance of a coprocessor
Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to...
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7418572 |
Pretranslating input/output buffers in environments with multiple page sizes
Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports...
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7409472 |
Device controller and input/output system
An input/output request sent from a host is once cued through a channel adapter and is then transferred to a resource manager and is cued, and the cuing is distributed. Even if sequential...
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7406569 |
Instruction cache way prediction for jump targets
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
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7398377 |
Apparatus and method for target address replacement in speculative branch target address cache
An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid...
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7389385 |
Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis
Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with...
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7386701 |
Prefetching hints
A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for...
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7383415 |
Hardware demapping of TLBs shared by multiple threads
In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one...
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7360058 |
System and method for generating effective address
Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes...
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7346755 |
Memory quality assurance
An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations....
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7340584 |
Sequential nibble burst ordering for data
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode...
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7334088 |
Page descriptors for prefetching and memory management
A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a...
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7328433 |
Methods and apparatus for reducing memory latency in a software application
Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce...
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7318142 |
System and method for dynamically adjusting read ahead values based upon memory usage
A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are...
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7305526 |
Method, system, and program for transferring data directed to virtual memory addresses to a device memory
Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device...
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7302527 |
Systems and methods for executing load instructions that avoid order violations
Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to...
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7296140 |
Prefetching data in a computer system
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector...
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7284112 |
Multiple page size address translation incorporating page size prediction
Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation...
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7240161 |
Instruction prefetch caching for remote memory
A disk drive control system comprising a micro-controller, a micro-controller cache system adapted to store micro-controller data for access by the micro-controller, a buffer manager adapted to...
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7238218 |
Memory prefetch method and system
Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are...
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7222219 |
Memory control method and memory control apparatus for pipeline processing
A signal generator detects a stage in which a central processing unit (CPU) reads an interrupt vector number from an instruction controller based on an address on an address bus and generates an...
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7181583 |
Method and program for creating a snapshot, and storage system
This invention includes: a step (S 1 ) of receiving a snapshot creation request from a client computer; a step (S 3 ) of obtaining, upon reception of the snapshot creation request, a usage ratio of...
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7165165 |
Anticipatory power control of memory
In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory...
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7159074 |
Data storage system
When replacing a disk device that has passed over a warranty expiration date with a new disk device, data necessary to be stored thereafter among the data that is recorded in the device must be...
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7133995 |
Dynamic page conflict prediction for DRAM
A memory controller may be implemented using dynamic page conflict prediction to control the closure of memory pages. A memory controller may include a page history register configured to store a...
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7133973 |
Arithmetic processor
An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the...
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7127586 |
Prefetching hints
A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for...
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7120753 |
System and method for dynamically adjusting read ahead values based upon memory usage
A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are...
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7117309 |
Method of detecting sequential workloads to increase host read throughput
Exemplary systems and methods analyze cache data to detect a sequential workload to facilitate pre-fetching effectiveness. An exemplary address analysis module for sequential workload detection...
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7099913 |
Speculative directory writes in a directory based cache coherent nonuniform memory access protocol
A system and method is disclosed that reduces the latency of directory updates in a directory based Distributed Shared Memory computer system by speculating the next directory state. The...
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