Matches 101 - 150 out of 247 < 1 2 3 4 5 >
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6701422 Memory control system with incrementer for generating speculative addresses  
A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to...
6694421 Cache memory bank access prediction  
A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache...
6687794 Prefetching mechanism for data caches  
A data structure to aid in and a method, system, and computer program product for prefetching data from a data cache are provided. In one embodiment, the data structure includes a prediction...
6684294 Using an access log for disk drive transactions  
A disk driver includes an access log for recording recent transactions with the hard disk drive. The access log may be consulted during write operations to buffer writes to memory before accessing...
6681178 Navigation apparatus  
When map data necessary for route guiding is pre-read from a map recording medium 101 , and accumulated in a data buffer, the quantity or the ratio of the pre-read data with respect to data...
6678815 Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end  
An apparatus and method for reducing power consumption in a processor front end are provided. The processor includes an instruction cache, a TLB, and a branch predictor. For sequential code...
6675282 System and method for employing a global bit for page sharing in a linear-addressed cache  
A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block,...
6675279 Behavioral memory enabled fetch prediction mechanism within a data processing system  
A behavioral memory mechanism for performing fetch prediction within a data processing system is disclosed. The data processing system includes a processor, a real memory, an address converter, a...
6675280 Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher  
A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized...
6662274 Method for using cache prefetch feature to improve garbage collection algorithm  
A method for creating a mark stack for use in a moving garbage collection algorithm is described. The algorithm of the present invention creates a mark stack to implement a MGCA. The algorithm...
6662286 Information processing method and information processing apparatus  
Memory corruption can be suppressed. When data stored in a random access area are read, the read data (physical block) are retrieved by a logic block number and newest data are read by referring to...
6647473 Kernel-based crash-consistency coordinator  
A snapshot system capable of capturing snapshots of multiple volumes wherein the snapshots are coordinated. A snapshot manager determines which volumes are to be involved in a snapshot operation,...
6647491 Hardware/software system for profiling instructions and selecting a trace using branch history information for branch predictions  
The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which...
6647464 System and method utilizing speculative cache access for improved performance  
A system and method are disclosed which provide a cache structure that allows early access to the cache structure's data. A cache design is disclosed that, in response to receiving a memory access...
6643739 Cache way prediction based on instruction base register  
A way prediction scheme for a partitioned cache is based on the contents of instructions that use indirect addressing to access data items in memory. The contents of indirect-address instructions...
6625696 Method and apparatus to adaptively predict data quantities for caching  
An apparatus and method for predicting quantities of data that will be requested by requesting devices capable of initiating requests for data from storage devices, in which prediction of...
6625712 Memory management table producing method and memory device  
The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information...
6615337 Method and apparatus for maintaining coherency in a translation lookaside buffer  
In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit...
6594730 Prefetch system for memory controller  
An embodiment of the present invention provides a memory controller that includes a plurality of transaction queues and an arbiter, a prefetch cache in communication with the arbiter, and a...
6581151 Apparatus and method for speculatively forwarding storehit data based on physical page index compare  
A speculative store forwarding apparatus in a pipelined microprocessor that supports paged virtual memory is disclosed. The apparatus includes comparators that compare only the physical page index...
6581140 Method and apparatus for improving access time in set-associative cache systems  
A system provides a method and apparatus for accessing information in a cache in a data processing system. The system optimizes a speed-critical path within the cache system by using a prediction...
6578130 Programmable data prefetch pacing  
A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to...
6571318 Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism  
A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry...
6564313 System and method for efficient instruction prefetching based on loop periods  
The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may...
6560689 TLB using region ID prevalidation  
A prevalidation content addressable memory, CAM, is used to pre-decode a virtual address region extension and enable it for use by a translation look-aside buffer, TLB. The prevalidation CAM...
6553476 Storage management based on predicted I/O execution times  
A storage apparatus has input means for inputting an input/output execution time prediction request from an external system and determining means for predicting the execution time of the...
6542891 Safe strength reduction for Java synchronized procedures  
The present invention is a computer implemented method and system for minimizing contention for a shared resource between a plurality of processes executing computer instructions that are...
6535962 System and method for prefetching data using a hardware prefetch mechanism  
A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory....
6523096 Apparatus for and method of accessing a storage region across a network  
N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon...
6496917 Method to reduce memory latencies by performing two levels of speculation  
A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a...
6480942 Synchronized FIFO memory circuit  
A synchronized FIFO memory circuit includes a random access memory and a FIFO controller having a decreased critical-path length. The synchronized FIFO circuit comprises a first counter for...
6470438 Methods and apparatus for reducing false hits in a non-tagged, n-way cache  
In one embodiment of the invention, each data value which is provided to a non-tagged, n-way cache is hashed with a number of bits which correspond to the data value, thereby producing a hashed...
6453411 System and method using a hardware embedded run-time optimizer  
The inventive mechanism has a run-time optimization system (RTOS) embedded in hardware. When the code is first moved into Icache, a threshold value is set into a counter associated with the...
6442658 Method and apparatus for improving playback of interactive multimedia works  
The present invention comprises a system for delivering an interactive multimedia work from a storage device, for example a hard disk drive, a CD-ROM drive, a network server, etc. to a playback...
6437531 Backup method of microcomputer used in case of stoppage of operation, backup unit of microcomputer, and control unit for controlling power window for automobile use  
There is provided an external watchdog timer 30 for detecting a temporary runaway of the microcomputer body 20 and resetting it according to a pulse output of the microcomputer body 20. ...
6438627 Lower address line prediction and substitution  
An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst...
6438656 Method and system for cancelling speculative cache prefetch requests  
A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an...
6427207 Result forwarding cache  
An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing—that are not...
6418525 Method and apparatus for reducing latency in set-associative caches using set prediction  
A method and apparatus for storing and utilizing set prediction information regarding which set of a set-associative memory will be accessed for enhancing performance of the set-associative memory...
6418530 Hardware/software system for instruction profiling and trace selection using branch history information for branch predictions  
The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which...
6415380 Speculative execution of a load instruction by associating the load instruction with a previously executed store instruction  
A processor having a data providing unit comprises a first table for holding the address of a store instruction indexed by a data address at which data value is stored by the store instruction, a...
6412059 Method and device for controlling cache memory  
In order to immediately respond to an access request from a processor with reduced power consumption, a requested information is read out from a cache memory 31 or information buffers 42 1 to ...
6412046 Verification of cache prefetch mechanism  
A method and apparatus automatically and easily verifies a cache line prefetch mechanism. The verification method includes a strict definition of which cache lines should be prefetched and which...
6385703 Speculative request pointer advance for fast back-to-back reads  
A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and,...
6353879 Memory address translation in a data processing system  
A data processing system 2 is provided with a processor core 4 that issues virtual addresses VA that are translated to mapped addresses MA by an address translation circuit 6 based upon a...
6351796 Methods and apparatus for increasing the efficiency of a higher level cache by selectively performing writes to the higher level cache  
Methods and apparatus for storing data in a multi-level memory hierarchy having at least a lower level cache and a higher level cache. Relevancy information is maintained for various data values...
6349358 Magnetic disc control apparatus capable of detecting a near sequential I/O and storing it to a cache memory, and a system thereof  
A magnetic disc control apparatus detects a near sequential I/O and pre-reads data from a magnetic disc drive into a cache memory. The control apparatus includes a near sequential I/O processor,...
6332187 Cumulative lookahead to eliminate chained dependencies  
A processor is configured to generate lookahead values using a cumulative constant. The processor classifies operations to a particular register (e.g. the stack pointer register, or ESP in an...
6330664 Method relating to handling of conditional jumps in a multi-stage pipeline arrangement  
An arrangement and a method provide instruction processing. Instructions are delivered to a multi-stage pipeline arrangement from at least one instruction source. A storing arrangement stores jump...
6329985 Method and apparatus for graphically displaying mapping of a logical object  
A method and apparatus for manipulating data in a storage device that is coupled to a host computer. Manipulations that can be performed by the storage device include moving non-contiguous blocks...
Matches 101 - 150 out of 247 < 1 2 3 4 5 >