|
Match
|
Document |
Document Title |
|
|
7620792 |
Processing system, memory and methods for use therewith
A memory includes an array of memory cells arranged in a plurality of rows and a plurality of columns. An address transform module receives a logical address including a logical column address and...
|
|
|
7620791 |
Mapping memory in a parallel processing environment
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
|
|
|
7620775 |
System and method for managing storage networks and providing virtualization of resources in such a network using one or more ASICs
This invention is a system and method for managing one or more data storage networks using a new architecture.
|
|
|
7620774 |
System and method for managing storage networks and providing virtualization of resources in such a network using one or more control path controllers with an embedded ASIC on each controller
This invention is a system and method for managing one or more data storage networks using a new architecture.
|
|
|
7620772 |
Methods and structure for dynamic data density in a dynamically mapped mass storage device
Methods and structures for dynamic density control to improve reliability of a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks...
|
|
|
7620766 |
Transparent sharing of memory pages using content comparison
A computer system has one or more software contexts that share use of a memory that is divided into units such as pages. In the preferred embodiment of the invention, the contexts are, or include,...
|
|
|
7617379 |
Multi-hit control method for shared TLB in a multiprocessor system
The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an...
|
|
|
7617377 |
Splitting endpoint address translation cache management responsibilities between a device driver and device driver services
Mechanisms for splitting responsibilities for communicating with an endpoint between a device driver and device driver services are provided. With these mechanisms, the device driver is responsible...
|
|
|
7617358 |
Methods and structure for writing lead-in sequences for head stability in a dynamically mapped mass storage device
Methods and structures for writing thermal lead-in sequences to provide head stability in a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied...
|
|
|
7617352 |
Memory controller, flash memory system having memory controller and method for controlling flash memory device
A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target...
|
|
|
7613881 |
Method and system for configuring and using virtual pointers to access one or more independent address spaces
System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless...
|
|
|
7610464 |
Methods and apparatus for providing independent logical address space and access management
A command receiver receives, from an external access requesting entity, a command with which to access data, together with an address to be accessed and IOID to identify the access requesting...
|
|
|
7610454 |
Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses
A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique...
|
|
|
7610435 |
Nonvolatile memory device employing a write completion flag table
A writing completion flag table that stores a writing completion flag corresponding to a predetermined storage, such as a cluster or a physical block, is stored in a non-volatile control memory....
|
|
|
7606993 |
Flash memory controller, memory control circuit, flash memory system, and method for controlling data exchange between host computer and flash memory
A controller included in a flash memory system, which can be applied to a memory interface of a host computer is disclosed. A buffer is used for data exchange operation between the host computer...
|
|
|
7606813 |
Model consolidation in a database schema
A database manager maintains information (in a database) associated with each of multiple resources according to different domain models used to view the resources by corresponding topology...
|
|
|
7603568 |
Method and apparatus for self-validating checksums in a file system
A method for storing a data block, involving storing the data block in a storage pool, obtaining a data block location, calculating a data block checksum for the data block, and storing a first...
|
|
|
7603538 |
Access environment construction system and method
Host environment information of the host is acquired from an environment management section that manages the host environment information, a designation of a volume condition constituting a...
|
|
|
7603530 |
Methods and structure for dynamic multiple indirections in a dynamically mapped mass storage device
Methods and structures for dynamic multiple indirections to improve reliability and performance of a dynamically mapped storage devices. In a dynamically mapped storage device in which all user...
|
|
|
7600093 |
Device, method and computer program product for multi-level address translation
A method for retrieving information from a storage unit, the method includes: receiving, by an input output memory management unit second-level translation information representative of a partition...
|
|
|
7600041 |
Industrial or domestic local network
The exchange of frames over a network between devices. Each device comprises a communication circuit connected to a processing unit and comprises addresses, each one being associated with a...
|
|
|
7596663 |
Identifying a cache way of a cache access request using information from the microtag and from the micro TLB
A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor;...
|
|
|
7596655 |
Flash storage system with data storage security
A flash storage comprises a flash memory, including a plurality of physical memory blocks, each of physical memory blocks comprising a plurality of memory segments, and a plurality of physical...
|
|
|
7596654 |
Virtual machine spanning multiple computers
In one embodiment, a virtual NUMA system may be formed from multiple computer systems coupled to a network such as InfiniBand, Ethernet, etc. Each computer includes one or more software modules...
|
|
|
7594092 |
Integrated multidimensional sorter
A technique to implement an integrated multidimensional sorter is to store data such that it may be retrieved in a sorted fashion. Entries are stored into a memory according to time stamp value,...
|
|
|
7594075 |
Metadata for a grid based data storage system
Metadata architecture and associated methodology for a data storage system employing a grid-based storage capacity wherein each grid defines a storage unit in terms of a plurality of storage...
|
|
|
7590818 |
Storage system having a plurality of virtualization apparatuses that allocate a storage area, form a plurality of virtual volumes, and process input-output from a host processor
In a storage system having a plurality of virtualization apparatuses that allocate a storage area which a storage device has, form a plurality of virtual volumes, and process input-output from a...
|
|
|
7590817 |
Communicating with an I/O device using a queue data structure and pre-translated addresses
Mechanisms for communicating with an I/O device or endpoint using a queue data structure and pre-translated addresses associated with the queue data structure are provided. With the mechanisms, a...
|
|
|
7590787 |
Apparatus and method for ordering transaction beats in a data transfer
A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response...
|
|
|
7587575 |
Communicating with a memory registration enabled adapter using cached address translations
Mechanisms for communicating with a memory registration enabled adapter, such as an InfiniBand™ host channel adapter, are provided. With the mechanisms, device driver services may be invoked by a...
|
|
|
7584341 |
Method for defragmenting of virtual volumes in a storage area network (SAN)
A defragmentation method and system to overcome fragmentation of virtual volumes in storage area networks (SANs). The method includes combining and migrating fragments of data spread over multiple...
|
|
|
7581077 |
Method and system for transferring data in a storage operation
The invention provides a system and method for storing a copy of data stored in an information store. In one embodiment, a data agent reads one or more blocks containing the data from the...
|
|
|
7581076 |
Methods and devices for treating and/or processing data
At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the...
|
|
|
7581056 |
Load balancing using distributed front end and back end virtualization engines
Methods and apparatus are provided for improving network virtualization in a storage area network. A virtualization engine is divided into a front end virtualization engine and a back end...
|
|
|
7577783 |
Portable data storage device and method of dynamic memory management therefor
A portable data storage device includes a first storage unit having a data storing zone and a reserved zone for bad blocks in the first storage unit, and a second storage unit having a look-up...
|
|
|
7577764 |
Method, system, and computer program product for virtual adapter destruction on a physical adapter that supports virtual adapters
A method, computer program product, and distributed data processing system for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter...
|
|
|
7570642 |
Method and apparatus for computing, storing, and multiplexing modified bytes in a packet router
A method for generating a modified packet for output from a router. First, a received packet is stored in one memory location. Modified bytes corresponding to the received packet are computed and...
|
|
|
7568083 |
Memory mapped register file and method for accessing the same
A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by...
|
|
|
7565509 |
Using limits on address translation to control access to an addressable entity
A data storage resource is identifiable by physical addresses, and optionally by a virtual address. A policy defines which resources are accessible and which resources are not accessible. A request...
|
|
|
7565502 |
System managing a plurality of virtual volumes and a virtual volume management method for the system
This invention provides a control technique of a data processing system, in which functions of a highly-functional high-performance storage system are achieved in an inexpensive storage system so...
|
|
|
7565460 |
Information processing apparatus and method for handling packet streams
A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the...
|
|
|
7558938 |
Memory bus encoding
Encoding of logical addresses LA upon an off-chip memory bus 22 is performed to produce encoded addresses EA. The portion of the logical address encoded LA [9:3] does not include the least...
|
|
|
7555641 |
Efficient resource mapping beyond installed memory space by analysis of boot target
An embodiment of the present invention is a technique to provide resource mapping. A boot target of a platform is analyzed to determine if the boot target supports address mapping of a platform...
|
|
|
7555591 |
Method and system of memory management
The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to the processor. The processor is...
|
|
|
7555579 |
Implementing FIFOs in shared memory using linked lists and interleaved linked lists
FIFOs may be implemented in shared memory using linked lists and interleaved linked lists such that any individual FIFO can dynamically use any free memory location. The system may be implemented...
|
|
|
7552319 |
Methods and apparatus to manage memory access
An example method involves detecting a memory relocation process and disabling memory access to a memory block in response to detecting the memory relocation process. The example method also...
|
|
|
7552308 |
Method and apparatus for temporary mapping of executable program segments
A computer implemented method, data processing system, and computer usable code are provided for managing memory use for program segments in an executable program. The process copies a set of...
|
|
|
7552272 |
Automated wear leveling in non-volatile storage systems
Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone,...
|
|
|
7548999 |
Chained hybrid input/output memory management unit
In one embodiment, an input/output (I/O) node comprises an I/O memory management unit (IOMMU) configured to translate memory requests. The I/O node is configured to couple to an interconnect and to...
|
|
|
7546440 |
Non-volatile memory devices and control and operation thereof
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase...
|