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6748512 |
Method and apparatus for mapping address space of integrated programmable devices within host system memory
A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
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6745266 |
Method and apparatus for disk cache translation between systems
A disk cache translation system for mapping data record lengths between systems having different data record lengths. Command queue ( 315 ) maps into initiation queue ( 305 ) to allow I/O manager (...
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6745284 |
Data storage subsystem including a storage disk array employing dynamic data striping
A data storage subsystem including a storage disk array employing dynamic data striping. A data storage subsystem includes a plurality of storage devices configured in an array and a storage...
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6742101 |
Scalable and flexible method for address space decoding in a multiple node computer system
A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address...
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6742081 |
Data storage array employing block checksums and dynamic striping
A storage system may include a plurality of storage devices each having a plurality of addressable locations for storing data. A storage controller may be coupled to the storage devices and...
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6738882 |
Concurrent multi-processor memory testing beyond 32-bit addresses
Memory about 4 Gbytes is tested using a DOS diagnostics program that remaps memory to a 32-bit addresses. In some embodiments, memory above 3 Gbytes is tested in 1 Gbyte blocks until the end of...
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6738887 |
Method and system for concurrent updating of a microcontroller's program memory
A system and method for concurrent operations in a microcontroller's program memory is provided. In one exemplary embodiment, a microcontroller system is provided that includes a microcontroller,...
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6735179 |
Systems and methods for packet filtering
Systems and methods are described for converting priority based rules into isomorphic longest match rules. Rules for packet processing may be presented to a networking device in priority order,...
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6731643 |
Method and apparatus for routing information packets associated to addresses represented through numerical strings
A method for routing information packets associated with addresses represented by numerical strings, in routing apparatuses for telecommunication networks, wherein the routing apparatus receives...
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6732250 |
Multiple address translations
A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation...
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6732251 |
Register file circuitry
A processor or processor core has register file circuitry having a plurality of physical registers and a plurality of tag storing portions corresponding respectively to the physical registers. Each...
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6732227 |
Network translation circuit and method using a segmentable content addressable memory
A translation circuit for translating addresses between computer networks and an associated method of performing address translation for a computer system are provided. The translation circuit...
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6732192 |
Disc recording scheme for enabling quick access to disc data
A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical...
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6728844 |
Method for preventing unauthorized access to storage volumes
N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30 ; upon...
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6728856 |
Modified Harvard architecture processor having program memory space mapped to data memory space
A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in...
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6727905 |
Image data processing apparatus
An image data processing apparatus capable of performing processing at a high speed comprising a DRAM for storing display data including a plurality of first pixel data respectively indicating...
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6728859 |
Programmable page table access
An apparatus and method are provided to enable programmable page table accesses in a virtual memory system. The apparatus includes context logic and context configuration logic. The context logic...
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6725322 |
Memory card, method for allotting logical address, and method for writing data
Blocks and clusters are brought to correspondence thereby to erase blocks of memory area efficiently. A flash memory has its physical addresses partitioned from address 0h sequentially into blocks...
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6725284 |
Logical partition hosted virtual input/output using shared translation control entries
The present invention provides a method for sharing I/O facilities among logical partitions. A remote translation control entry table is created on a hosted partition appearing to own a virtual...
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6725329 |
Cache control system and method having hardware-based tag record allocation
The present invention relates to a disk drive 10 comprising a cache memory 14 and a cache control system having a tag memory having a plurality of tag records, and means for allocating a tag...
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6725298 |
Method and system for filter-processing by ensuring a memory space for a ring-buffer in digital signal processor
A method of managing ring-buffer memory space in a digital signal processor when processing a filter, includes releasing ring-buffer memory space previously reserved for ring-buffer data upon...
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6725288 |
System for transmitting data between a device data area and a variable data area of a memory according to a memory map based on an identifying data of a device detected
A controller contains an I/O memory and uses a device detecting service to detect a device connected to it through a network and to obtain its device identifying data. A memory map setting service...
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6725289 |
Transparent address remapping for high-speed I/O
A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region....
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6721869 |
Method for deriving a word address and byte offset information
A method for addressing a particular location of a memory organized as a plurality of words having an odd number (e.g., three) partitions. Upon receiving an address for a particular memory...
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6721868 |
Redirecting memory accesses for headless systems
Redirection of accesses to non-existent memory is instead sent to a virtual buffer. The virtual buffer may be implemented in headless systems which include no video buffer. Console redirection may...
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6718451 |
Utilizing overhead in fixed length memory block pools
A method of managing a fixed length memory block pool having a plurality of memory blocks includes receiving a memory block address from a memory management module, in which the memory block...
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6711661 |
Method and apparatus for performing hierarchical address translation
A method and a device for translating a hierarchical address, the device is adapted to receive a destination address, to search an array of sorted binary string being associated with a group of...
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6711673 |
Using a model specific register as a base I/O address register for embedded I/O registers in a processor
A processor includes an input/output (I/O) register that is mapped into input/output (I/O) address space. The processor also includes a base address register that is loaded with a base address. The...
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6708265 |
Method and apparatus for moving accesses to logical entities from one storage element to another storage element in a computer storage system
Methods and apparatus are disclosed for moving logical entities from one storage element to another storage element. Movement of the logical entity may be accomplished by using a logical volume...
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6704834 |
Memory with vectorial access
A parallel memory configured to enable access to a table with aligned and equidistant components constituting a vector of N components. The memory ( 1 ) is organized as M memory banks ( 8 ). Each...
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6701418 |
Automatic detection and correction of relatively rearranged and/or inverted data and address signals to shared memory
A set of related methods for detecting the existence and exact nature of any rearrangements and/or inversions of address lines and/or data lines to a memory device, relative to a second set of...
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6697881 |
Method and system for efficient format, read, write, and initial copy processing involving sparse logical units
A method and system for eliminating null I/O operations that transfer null data during processing of FORMAT and INITIAL-COPY I/O device commands and READ and WRITE I/O requests by an I/O device....
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6697076 |
Method and apparatus for address re-mapping
Methods and apparatuses for mapping a logical address to a physical address, in a data processing system having at least one host processor with host processor cache and host memory. In one aspect...
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6697367 |
Multihop system calls
A computer system may include one or more hosts and a plurality of data storage devices for providing multihop system calls. The data storage devices are interconnected and also connected to the...
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6694407 |
Cache memory with data transfer control and method of operating same
A cache memory ( 35 ) has a logical organisation in which its memory space is divided into sub-sections or partitions (P). This permits different data objects to be allocated to different...
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6687805 |
Method and system for logical-object-to-physical-location translation and physical separation of logical objects
A method and system for providing to a human user or high-level application program a functional interface for translating the names of logical objects into physical mappings of logical objects to...
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6687808 |
Data processor using indirect register addressing
A data processor is composed of a register file including a plurality of registers each of which stores therein an operand data, a register pointer section which includes a plurality of register...
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6687783 |
Access apparatus and method for accessing a plurality of storage device having different characteristics
When a storage medium is set in a control unit, a controller reads out device ID data, CIS data and Identify-Drive data from the storage medium. Based on the device ID data and the CIS data, the...
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6684309 |
Method for controlling access to data by redirecting modifications of the data
There is disclosed a method and apparatus for controlling access to and corruption of information in a computer system. In known “PC Virus” protection methods the boot partition becomes “Read...
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6684313 |
Managing storage contention in automated storage systems
An automated process of assigning storage resources to logical units (“LU's”) is informed of contention avoidance, in order to yield reduced contention. LU's are defined and assigned to logical...
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6684291 |
Interface for a memory, and method for variable configuration of a memory apparatus
A memory including a plurality of memory cells combined into multiple physical sectors, in which the memory cells combined into one physical sector are capable of being erased only together, and in...
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6681310 |
Storage management system having common volume manager
A storage management system in which a plurality of volume providers maps logical storage volumes onto one or more storage devices within a stand-alone computer or within a storage network. A...
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6681305 |
Method for operating system support for memory compression
In a system with hardware main memory compression, the method of this invention monitors the physical memory utilization and if physical memory is near exhaustion it forces memory to be paged out,...
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6680870 |
Memory device, data processing method and data processing program
A memory device that is free from problems resulted from the characteristics of nonvolatile memory chips. The problems are specifically those occurring at the time of data transfer between...
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6678722 |
Interprocessor communication system for parallel processing
The present invention is directed to providing an interprocessor communication system capable of obviating degradation of the performance in an interprocessor communication caused by the processing...
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6675282 |
System and method for employing a global bit for page sharing in a linear-addressed cache
A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block,...
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6675277 |
Method and apparatus for demand usable adapter memory access management
A method and apparatus for using a memory adapter may allow a system to access the memory adapter. The memory adapter may comprise a list of entries for data within the memory adapter. Each entry...
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6675279 |
Behavioral memory enabled fetch prediction mechanism within a data processing system
A behavioral memory mechanism for performing fetch prediction within a data processing system is disclosed. The data processing system includes a processor, a real memory, an address converter, a...
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6675274 |
Method and apparatus for determining volume swaps
Described are techniques for determining temporary storage areas for logical volumes to be swapped. Logical volumes may be swapped in a computer system in connection with efforts to improve...
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6671776 |
Method and system for determining and displaying the topology of a storage array network having multiple hosts and computer readable medium for generating the topology
A system and method for dynamically generating the topology of a storage array network by linking information concerning hosts and clusters along with information about host port adapters. Namely,...
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