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7610518 |
Program counter range comparator with equality, greater than, less than and non-equal detection modes
An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on...
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7610469 |
Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the...
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7587535 |
Data transfer control device including endian conversion circuit with data realignment
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
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7583732 |
Managing bursts of data
Bursts of data are managed. Data is stored in a machine readable memory device a first time at a first memory address. The machine readable memory device has one or more burst boundaries. The first...
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7571299 |
Methods and arrangements for inserting values in hash tables
Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in...
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7546438 |
Algorithm mapping, specialized instructions and architecture features for smart memory computing
A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like...
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7509640 |
Task distribution in computing architectures
Task distribution is performed in hardware without the use of “division” logic component to divide executions between task execution registers, which advantageously require less silicon when...
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7493442 |
Multiple segment data object management
A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index table objects containing defining...
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7484069 |
Watchpointing unaligned data accesses
A data processing system incorporating watchpoint registers is provided. The memory accesses to be detected may be unaligned memory accesses. The watchpoint may operate in a normal mode and also in...
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7484049 |
Data storage system packer/depacker
A system for aggregating portions of multiple blocks of data into a single composite block. The block of data comprises different packets of data stored in correspondingly different sections of a...
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7480783 |
Systems for loading unaligned words and methods of operating the same
Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a...
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7480781 |
Apparatus and method to merge and align data from distributed memory controllers
We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory...
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7472250 |
Storage control device, and control method for storage control device
The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks,...
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7467381 |
Resource partitioning and direct access utilizing hardware support for virtualization
The present disclosure relates to the resource management of virtual machine(s) using hardware address mapping, and, more specifically, to facilitate direct access to devices from virtual machines,...
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7447876 |
System and method for handling load and/or store operations in a superscalar microprocessor
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
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7421561 |
Instruction set for efficient bit stream and byte stream I/O
A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including...
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7412584 |
Data alignment micro-architecture systems and methods
Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic...
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7404042 |
Handling cache miss in an instruction crossing a cache line boundary
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process...
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7401202 |
Memory addressing
Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to...
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7395404 |
Cluster auto-alignment for storing addressable data packets in a non-volatile memory array
Alignment of clusters to pages is provided in a non-volatile memory system that receives data from a host in clusters and writes data to a memory array in units of a page. Alignment is implemented...
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7380084 |
Dynamic detection of block boundaries on memory reads
In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for...
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7366819 |
Fast unaligned cache access system and method
A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple...
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7362833 |
Dynamic special character selection for use in byte alignment circuitry
Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When...
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7360055 |
Two address map for transactions between an X-bit processor and a Y-bit wide memory
Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises a first address space, a second...
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7356664 |
Method and apparatus for transferring data from a memory subsystem to a network adapter for improving the memory subsystem and PCI bus efficiency
A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting...
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7319702 |
Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments
A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the...
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7310337 |
Packet header alignment
According to some embodiments, a network layer header of a network packet is received, metadata associated with the network packet is received, a header offset associated with the network packet is...
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7302545 |
Method and system for fast data access using a memory array
First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable...
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7302525 |
Method and apparatus for efficiently accessing both aligned and unaligned data from a memory
A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the...
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7296135 |
Data misalignment detection and correction in a computer system utilizing a mass storage subsystem
An embodiment of a data misalignment correction method for a mass storage drive array subsystem coupled to a computer operating system having input/output data block requests is provided. The data...
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7296134 |
Fast unaligned memory access system and method
A microprocessor system includes an address generator, an address selector, and memory system having multiple memory towers, which can be independently addressed. The address generator...
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7296108 |
Apparatus and method for efficient transmission of unaligned data
An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment...
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7278030 |
Virtualization system for computers having multiple protection mechanisms
In a virtual computer system, the invention virtualizes a primary protection mechanism, which restricts memory accesses based on the type of access attempted and a current hardware privilege level,...
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7231505 |
Aligning IP payloads on memory boundaries for improved performance at a switch
A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Inernet Protocol)...
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7210023 |
Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address
The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of...
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7194574 |
Searching small entities in a wide CAM
A plurality of entities are stored in a single addressable location in a Content Addressable Memory (CAM). A column in a CAM entry is selected for storing an entity based on the property of the...
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7188231 |
Multimedia address generator
Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with...
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7167968 |
Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data
A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between...
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7162491 |
Data processing system, data processing method and computer program
The present invention is to provide a system capable of preventing an increase in load even if the amount of data increases. Upon receipt of a retrieval request, a main control part specifies, from...
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7136985 |
Method and system for fast data access using a memory array
First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable...
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7134001 |
Pipeline replay support for unaligned memory operations
Instructions asserted in a microprocessors instruction pipeline ( 3 ) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline ( 5 ) that...
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7120781 |
General purpose register file architecture for aligned simd
A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture...
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7111122 |
Access circuit with various access data units
An access circuit for efficiently accessing a buffer memory in accordance with an instruction from an external circuit. An access data unit for accessing a SDRAM in one operation clock cycle of the...
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7107429 |
Data access in a processor
A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in...
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7089394 |
Optimally mapping a memory device
In one embodiment of the present invention, a method includes observing disk requests for a drive associated with a memory device; and mapping the memory device based on observing the disk requests.
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7089393 |
Data processing using a coprocessor
A data processing system using a main processor 8 and a coprocessor 10 provides coprocessor load instructions (USALD) for loading a variable number of data values dependent upon alignment into...
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7085911 |
Resizable cache sensitive hash table
A hash table for a collection of data items includes a set of hash buckets, each hash bucket being associated with a subset of the collection of data items, and a set of properties entries in each...
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7076631 |
Mechanism for on-the-fly handling of unaligned memory accesses
Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner,...
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7065625 |
Computer system, method, and program product for performing a data access from low-level code
A computer system includes a register that is configured to contain a zero value. In response to a predetermined occurrence on the computer system, such as a hardware interrupt, the computer system...
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7043618 |
System for memory access in a data processor
A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in...
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