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7624256 |
System and method wherein conditional instructions unconditionally provide output
A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not...
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7620838 |
Semiconductor integrated circuit and image processing system using the same
A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the...
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7620789 |
Out of order DRAM sequencer
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the...
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7620788 |
Memory device sequencer and method supporting multiple memory device clock speeds
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads...
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7603536 |
Data processing apparatus and image reading apparatus
A data processing apparatus includes a data processing section that issues a plurality of data transfer requests simultaneously; an internal memory provided inside a circuit including the data...
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7603535 |
Low power consumption semiconductor memory device capable of selectively changing input/output data width and data input/output method
A semiconductor memory device includes a memory cell core having a plurality of memory cells; a data input/output circuit unit, which sets an input/output data width in response to input/output...
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7594087 |
System and method for writing data to and erasing data from non-volatile memory
A method and system for accessing a non-volatile memory is disclosed. The method includes writing a first stream of data to a first block of a first region of a non-volatile memory and detecting a...
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7594080 |
Temporary storage of memory line while waiting for cache eviction
The temporary storage of a memory line to be stored in a cache while waiting for another memory line to be evicted from the cache is disclosed. A method includes evicting a first memory line...
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7594079 |
Data cache virtual hint way prediction, and applications thereof
A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way...
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RE40921 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it...
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7584340 |
System and method for pre-provisioning storage in a networked environment
System and method for pre-provisioning data storage in a network storage environment. Embodiments may pre-provision more storage than needed and make the spare storage available to two or more...
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7552301 |
Information processing apparatus and memory access arranging method
An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control...
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7552255 |
Dynamically partitioning pipeline resources
In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing...
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7552254 |
Associating address space identifiers with active contexts
In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space...
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7529908 |
Method and apparatus for unified exception handling with distributed exception identification
A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for...
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7526604 |
Command queueing speculative write prefetch
Method and apparatus for improving system performance using controlled speculative write prefetching in systems that use command queuing. Speculative write prefetching can be forced on or off, or a...
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7523230 |
Device and method for maximizing performance on a memory interface with a variable number of channels
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
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7519779 |
Dumping using limited system address space
Method and apparatus for reading the internal address space of an adapter in a system during a dump are described. The adapter includes a control port and a data port used as channels for...
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7515482 |
Pipe latch device of semiconductor memory device
A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating...
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7512763 |
Transparent SDRAM in an embedded environment
A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part...
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7511851 |
Method of and apparatus for forming an image, and computer program
The network printer obtains information from a Web page over the network, and stores this obtained information together with a URL thereof and the time when this information was received into the...
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7509469 |
Semiconductor memory asynchronous pipeline
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous...
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7508397 |
Rendering of disjoint and overlapping blits
Methods, apparatuses, and systems are presented for modifying data in memory associated with an image, involving processing data operations in a pipelined process affecting data in memory...
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7490210 |
System and method for processor with predictive memory retrieval assist
A system and method for memory control. The system includes a hard-IP memory controller, a soft-IP frequency conversion system, and an interface system. The soft-IP frequency conversion system is...
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7490187 |
Hypertransport/SPI-4 interface supporting configurable deskewing
A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain....
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7490186 |
Memory system having an apportionable data bus and daisy chained memory chips
A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain....
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7487318 |
Managing write-to-read turnarounds in an early read after write memory system
Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read...
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7487317 |
Cache-aware scheduling for a chip multithreading processor
A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is...
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7487302 |
Service layer architecture for memory access system and method
A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is...
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7478215 |
Multi-controller write operations
A system and method for high performance multi-controller processing is disclosed. Independent Network storage controllers (NSCs) are connected by a high-speed data link. The NSCs control a...
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7478189 |
Deadlock avoidance in a bus fabric
Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a...
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7467256 |
Processor having content addressable memory for block-based queue structures
Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue...
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7466607 |
Memory access system and method using de-coupled read and write circuits
A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit...
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7464242 |
Method of load/store dependencies detection with dynamically changing address length
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
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7461199 |
Pipelined parallel programming operation in a non-volatile memory system
The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to...
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7461180 |
Method and apparatus for synchronizing use of buffer descriptor entries for shared data packets in memory
Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned...
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7457615 |
Method for processing query effectively in radio data broadcast environment
A method for processing query effectively in a radio data broadcast environment is able to minimize a query response time by pre-declaring data items which are wanted to be accessed by a mobile...
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7454579 |
Managing access to shared resources
Managing access to a shared resource includes receiving a request indicating that an operation requires access to the shared resource, associating the operation with a lock in a lock queue that is...
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7454563 |
Buffer management device, record and reproduction apparatus and management method for buffer memory
A buffer management device of record and reproduction apparatus for an optical storage medium and a management method for a buffer memory are provided. By employing two sets of pointers to manage...
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7450440 |
Circuit for initializing a pipe latch unit in a semiconductor memory device
A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the...
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7447805 |
Buffer chip and method for controlling one or more memory arrangements
A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received...
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7444488 |
Method and programmable unit for bit field shifting
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first...
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7426621 |
Memory access request arbitration
A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The...
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7421559 |
Apparatus and method for a synchronous multi-port memory
A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access...
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7421557 |
Method and device for performing cache reading
Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH...
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7418543 |
Processor having content addressable memory with command ordering
A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to...
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7418540 |
Memory controller with command queue look-ahead
In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random...
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7409516 |
Pending request scoreboard for out-of-order memory scheduler
Embodiments of a memory scoreboard are presented herein. The memory scoreboard tracks memory requests for each rank and bank of memory being addressed. When there are no pending requests, the...
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7395399 |
Control circuit to enable high data rate access to a DRAM with a plurality of areas
A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write...
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7392362 |
System and method for volume management
A volume management system includes a management server which includes a memory and a processor, the memory stores an area level indicative of released or unreleased, a priority level indicative of...
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