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7613886 |
Methods and apparatus for synchronizing data access to a local memory in a multi-processor system
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
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7613866 |
Method for controlling access to a multibank memory
The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording...
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7610447 |
Upgradable memory system with reconfigurable interconnect
Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the...
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7610200 |
System and method for controlling sound data
A system and method for controlling access to parameter blocks of a sound processor. According to the method and system disclosed herein, the present invention includes a host, a sound processor...
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7607134 |
Efficient serialization of bursty out-of-order results
A method, apparatus, and computer program product includes serially receiving, from a source, a plurality of forward messages each addressed to one of a plurality of destinations; receiving a...
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7603534 |
Synchronous flash memory with status burst output
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication...
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7596669 |
Apparatus and method for managing memory in a network switch
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a...
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7594089 |
Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of...
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7590811 |
Methods and system for improving data and application availability in clusters
Methods and systems are disclosed that relate to making back-up data available to a host server. An exemplary method includes making primary and secondary data volumes accessible to a first server...
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7577789 |
Upgradable memory system with reconfigurable interconnect
Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail...
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7577774 |
Independent source read and destination write enhanced DMA
The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to...
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7558934 |
Data storage unit, data storage controlling apparatus and method, and data storage controlling program
A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the...
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7558933 |
Synchronous dynamic random access memory interface and method
A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates...
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7552301 |
Information processing apparatus and memory access arranging method
An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control...
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7552247 |
Increased computer peripheral throughput by using data available withholding
A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and...
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7549013 |
Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector...
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7546416 |
Method for substantially uninterrupted cache readout
A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device...
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7535592 |
Image processing apparatus for simultaneous processing of a plurality of print data
This invention relates to an image processing apparatus capable of processing plural jobs at a high rate. The image processing apparatus is comprised of first and second buffer memory devices,...
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7533232 |
Accessing data from different memory locations in the same cycle
In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However,...
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7529896 |
Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules
A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first...
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7529886 |
Method, system and storage medium for lockless InfiniBand™ poll for I/O completion
A method, system, and storage medium for the InfiniBand™ Poll verb to support a multi-threaded environment without the use of kernel services to provide serialization for mainline Poll logic....
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7526626 |
Memory controller configurable to allow bandwidth/latency tradeoff
A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled...
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7523270 |
Multi-port memory device
A multi-port memory device has a plurality of ports which are connected to different external devices with the memory device performing serial data communication independently. The memory device...
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7523255 |
Method and apparatus for efficient storage and retrieval of multiple content streams
Embodiments of the present invention provide disk controller operable to facilitate the efficient storage and retrieval of multiple content (data) streams to magnetic disk media. This disk...
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7523250 |
Semiconductor memory system and semiconductor memory chip
A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip...
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7515500 |
Memory device performance enhancement through pre-erase mechanism
The specification and drawings present a new method, apparatus and software product for performance enhancement of a memory device (e.g., a memory card) using a pre-erase mechanism. The memory...
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7512766 |
Controlling preemptive work balancing in data storage
A storage network control apparatus is operable to present virtualized storage to a host system and includes a monitoring component, an analysis component, a detection component, and a migration...
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7512763 |
Transparent SDRAM in an embedded environment
A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part...
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7512756 |
Performance improvement for block span replication
The portion of a source block storage resource to be replicated, and the corresponding portion of the block storage resource being written to, are each divided into a predefined number of...
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7512747 |
Method and apparatus for efficiently supporting multiple one-time table access operations in a hierarchical memory setting
An embodiment of the present invention provides a computer system including a first memory and a second memory, where the first memory is substantially faster than the second memory. A method...
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7508397 |
Rendering of disjoint and overlapping blits
Methods, apparatuses, and systems are presented for modifying data in memory associated with an image, involving processing data operations in a pipelined process affecting data in memory...
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7505890 |
Hard disk drive emulator
A hard disk drive (HDD) emulator comprises a dynamic random access memory, a controller that refreshes content of the dynamic random access memory, and an input/output port coupled to the...
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7505356 |
Multi-column addressing mode memory system including an integrated circuit memory device
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
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7500075 |
Mechanism for enabling full data bus utilization without increasing data granularity
A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is...
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7487317 |
Cache-aware scheduling for a chip multithreading processor
A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is...
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7487316 |
Archive and restore system and methodology for on-line edits utilizing non-volatile buffering
The present invention relates to a system and methodology to mitigate memory current requirements in an industrial controller and to facilitate efficient on-line editing, storage and retrieval of...
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7487302 |
Service layer architecture for memory access system and method
A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is...
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7484028 |
Burst-capable bus bridges for coupling devices to interface buses
Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device....
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7478231 |
Storage control apparatus
In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying...
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7475210 |
Data stream generation method for enabling high-speed memory access
An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit...
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7475182 |
System-on-a-chip mixed bus architecture
A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could...
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7472236 |
Managing mirrored memory transactions and error recovery
In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In...
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7469308 |
Hierarchical bus structure and memory access protocol for multiprocessor systems
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus...
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7467265 |
System and method for block conflict resolution within consistency interval marker based replication
One goal of consistency interval replication is to achieve a consistent copy of data generated by independent streams of writes from nodes in a clustered/distributed environment. Two writes to the...
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7467261 |
Dual storage apparatus and control method for the dual storage apparatus
A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the...
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7466607 |
Memory access system and method using de-coupled read and write circuits
A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit...
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7464241 |
Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding
Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user...
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7461199 |
Pipelined parallel programming operation in a non-volatile memory system
The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to...
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7454599 |
Selecting multiple threads for substantially concurrent processing
The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for...
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7454563 |
Buffer management device, record and reproduction apparatus and management method for buffer memory
A buffer management device of record and reproduction apparatus for an optical storage medium and a management method for a buffer memory are provided. By employing two sets of pointers to manage...
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