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7620789 |
Out of order DRAM sequencer
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the...
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7620788 |
Memory device sequencer and method supporting multiple memory device clock speeds
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads...
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7620038 |
Using hot swap logic in a communication system
Methods and systems are provided for providing hot swapability of TSIs in a TDM system using FPGA hot swap logic. The hot swap logic is used to provide isolation for the TSIs from a system TDM bus...
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7617372 |
Avoiding copy on first write
Handling a write operation to write data to a section of a storage device includes determining if the section needs to be copied to at least a first target device and, if the section of the storage...
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7617354 |
Abbreviated burst data transfers for semiconductor memory
An integrated circuit having a nominal minimum burst length defined by a nominal data prefetch size transfers data by accepting an abbreviated burst data read request directed to a first bank,...
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7613961 |
CPU register diagnostic testing
One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of...
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7613883 |
Memory device with mode-selectable prefetch and clock-to-core timing
In a memory device, either a first portion or a second, smaller portion of data retrieved from a storage array is loaded into a data buffer in accordance with a prefetch mode selection and then...
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7607579 |
Information processing apparatus
The invention provides an information processing apparatus that includes: a card slot in which a card-type medium is inserted; and a data communication unit that performs data exchange with the...
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7606991 |
Dynamic clock switch mechanism for memories to improve performance
This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation will occur. The dynamic extension of...
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7603534 |
Synchronous flash memory with status burst output
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication...
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7603533 |
System and method for data protection on a storage medium
A method of and system for protecting a disk drive or other data storage includes mounting a virtual storage that combines a full access temporary storage and a READ-only portion of a main storage,...
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7603512 |
Dynamic memory refresh controller, memory system including the same and method of controlling refresh of dynamic memory
A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a...
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7600091 |
Executing background writes to idle DIMMS
Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers...
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7600090 |
Microcontroller based flash memory digital controller system
A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash...
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7600078 |
Speculatively performing read transactions
In one embodiment, the present invention includes a method for speculatively providing a read request to a memory controller associated with a processor, determining coherency of the read request...
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7596707 |
System and method for efficient power throttling in multiprocessor chip
A method for limiting power consumption in a multiprocessor chip is provided. In this method, a read or write request is received by the memory controller, which controls a memory that is external...
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7596669 |
Apparatus and method for managing memory in a network switch
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a...
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7594089 |
Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of...
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7594088 |
System and method for an asynchronous data buffer having buffer write and read pointers
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A...
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7594072 |
Method and apparatus incorporating virtualization for data storage and protection
A virtualization apparatus presents a virtual volume to a computer that stores data to the virtual volume. The data is stored by the virtualization apparatus to a first logical volume at a first...
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7590806 |
Filtering of transactional memory operations using associative tables
A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to achieve efficient performance. The...
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7590789 |
Optimizing clock crossing and data path latency
In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct...
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7587566 |
Realtime memory management via locking realtime threads and related data structures
The present invention is directed to a method and system for minimizing memory access latency during realtime processing. The method includes a mechanism for marking information that will be...
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7587547 |
Dynamic update adaptive idle timer
The invention describes a technology for closing DRAM pages, wherein the invention allows for dynamically changing code streams by tracking the previous decisions made on page closes and adjusts...
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7587310 |
Sound processor architecture using single port memory unit
A system and method for implementing a sound processor. The sound processor includes a first voice engine, a second voice engine, and at least one single-port memory unit. An operation of the first...
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7586800 |
Memory timing apparatus and associated methods
A computer memory includes a primary self-timing signal path defined by a model wordline signal path and a model bitline signal pair path. The primary self-timing signal path is defined to generate...
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7584335 |
Methods and arrangements for hybrid data storage
Embodiments may comprise a hybrid memory controller to facilitate accesses of more than on type of memory device, referred to generally hereafter as a hybrid memory device or hybrid cache device....
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7581121 |
System for a memory device having a power down mode and method
A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is...
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7580465 |
Low speed access to DRAM
Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a...
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7577811 |
Memory controller for daisy chained self timed memory chips
A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips...
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7577049 |
Speculative sense enable tuning apparatus and associated methods
A computer memory includes a sense enable control module for generating a sense enable signal for a memory core. The sense enable control module includes an active side for transmitting the sense...
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7574616 |
Memory device having a power down exit register
A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when...
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7574567 |
Monitoring processes in a non-uniform memory access (NUMA) computer system
A monitoring process for a NUMA system collects data from multiple monitored threads executing in different nodes of the system. The monitoring process executes on different processors in different...
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7574548 |
Dynamic data transfer control method and apparatus for shared SMP computer systems
As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there...
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7571330 |
System and module including a memory device having a power down mode
A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a...
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7571297 |
Data invalid signal for non-deterministic latency in a memory system
An apparatus, system, and method for a data invalid signal for non-deterministic latency in memory are described. The apparatus may include a memory to determine that data to be buffered for a data...
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7571296 |
Memory controller-adaptive 1T/2T timing control
Circuits, methods, and apparatus that adaptively control 1 T and 2 T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as...
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7571279 |
Accessing a disk drive at multiple speeds
A disk drive apparatus has a magnetic platter, a disk drive motor, and a disk drive controller. The disk drive controller is capable of storing data onto and retrieving data from the magnetic...
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7562185 |
Accessing a storage medium using dynamic read statistics
A method and system for accessing a storage medium that factors in read statistics of previous reads of the storage medium is provided. An access system tracks read statistics generated from...
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7561529 |
Optimizing the speed of an FC-AL switch domain in a data storage network
In a fibre channel, arbitrated loop (FC-AL) network environment, an operating speed of devices within a switch domain within the network is optimized. The FC-AL switch domain is isolated from an...
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7558934 |
Data storage unit, data storage controlling apparatus and method, and data storage controlling program
A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the...
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7558932 |
Semiconductor memory device and method for operating the same
A read command AL shifting unit shifts a read command for a predetermined additive latency, to output a shifted read command. A write command AL shifting unit shifts a write command for the...
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7558924 |
Systems and methods for accessing memory cells
Systems and methods for accessing data in a memory, where a register is provided to temporarily store data from a write operation and to make the data available for read operations that are...
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7558918 |
System for handling streaming information using a plurality of reader modules by enumerating output pins and associated streams of information
An information appliance receives streaming information. The information appliance includes a storage buffer and a writer module which receives the streaming information and writes the streaming...
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7555670 |
Clocking architecture using a bidirectional clock port
Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional...
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7552303 |
Memory pacing
A method, system, and program for managing memory page requests in a multi-processor data processing system determines a threshold value of available memory, and dynamically adjusts an allocation...
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7552302 |
Ordering operation
Executing an ordering operation is disclosed. A store operation associated with storing a value into a portion of a memory is initiated. An ordering operation to ensure that the store operation,...
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7552301 |
Information processing apparatus and memory access arranging method
An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control...
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7549033 |
Dual edge command
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of...
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7546435 |
Dynamic command and/or address mirroring system and method for memory modules
A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored...
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