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7404057 System and method for enhancing read performance of a memory storage system including fully buffered dual in-line memory modules  
A system and method for enhanced read performance of a memory storage system is disclosed. The storage system includes a first memory controller. At least one first channel of a plurality of memory...
7398367 Storage subsystem that connects fibre channel and supports online backup  
A disk array connected to a storage area network via a fibre channel has one or more ports each controlled by a processor. Even the disk array with one port and one processor executes online...
7395398 Memory controller that selectively changes frequency of a memory clock signal, a smart card including the same, and a method of controlling a read operation of a memory  
Provided are a memory controller that selectively changes a frequency of a memory clock signal, a smart card including the memory controller, and a method of controlling a read operation of a...
7389396 Bounding I/O service time  
A storage system with an array of redundant storage devices places bounds on access request servicing. If a storage device is unable to service the access request within the bounds, the storage...
7386696 Semiconductor memory module  
The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and...
7383408 Storage device that uses virtual ordered writes  
Ordering data writes include a host computer providing a plurality of data writes to a primary storage device, the primary storage device assigning a first sequence number to data writes begun...
7383396 Method and apparatus for monitoring processes in a non-uniform memory access (NUMA) computer system  
A monitoring process for a NUMA system collects data from multiple monitored threads executing in different nodes of the system. The monitoring process executes on different processors in different...
7383361 Disk array system and interface converter  
The present invention aims to provide a high-reliability, low-cost disk array by emulating an ATA drive so that it can be used in the same way as an FC drive. To achieve this object, a disk array...
7380084 Dynamic detection of block boundaries on memory reads  
In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for...
7380083 Memory controller capable of locating an open command cycle to issue a precharge packet  
A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In...
7380062 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch  
A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the...
7379453 Method and apparatus for transferring multiple packets from hardware  
A method and apparatus for facilitating transfer of packets from communication hardware to a host computing device or software. After receiving s set of packets at a communication interface, the...
7376950 Signal aggregation  
The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most...
7376802 Memory arrangement  
The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the...
7373471 Executing background writes to idle DIMMs  
Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers...
7370170 Data mask as write-training feedback flag  
Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the...
7370169 Efficient memory controller  
An efficient memory controller. The controller includes a first mechanism for associating one or more input command sequences with one or more corresponding values. A second mechanism selectively...
7370168 Memory card conforming to a multiple operation standards  
The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD card....
7370167 Time slicing device for shared resources and method for operating the same  
Broadly speaking, a device for addressing a shared resource is disclosed. The device includes at least one register in communication with the shared resource. The at least one register is...
7366863 Memory control apparatus, the program and method, and reproduction apparatus  
A reproduction apparatus capable of saving power consumption, wherein starting time data of a hard disk drive (HDD), is detected every time the HDD starts and, based on threshold value data...
7366862 Method and apparatus for self-adjusting input delay in DDR-based memory systems  
A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands....
7366843 Computer system implementing synchronized broadcast using timestamps  
A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by...
7366834 System and method for record retention date in a write once read many storage system  
This invention provides a specified retention date within a data set that is locked against deletion or modification within a WORM storage implementation. This retention date scheme does not...
7366828 Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device  
A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that...
7366827 Method and apparatus for selectively transmitting command signal and address signal  
A method for transmitting a command signal and an address signal to a rank which is to be accessed includes receiving and buffering the command signal and the address signal, and transmitting the...
7366822 Semiconductor memory device capable of reading and writing data at the same time  
A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are...
7366784 System and method for providing and using a VLAN-aware storage device  
The present invention provides secure IP protocol capable storage devices using Virtual Local Area Network (VLAN) techniques. Specific embodiments of the present invention provide techniques for...
7363451 Load balancing of disk drives  
System and methods are disclosed for load balancing Input/Output (IO) commands to be executed by one or more disk drives from an array of disk drives. Systems and methods disclosed herein use one...
7363450 Method and apparatus for estimating multithreaded processor throughput based on processor cache performance  
An estimate is calculated of the throughput of a multi-threaded processor having N threads based on measured miss rates of a cache memory associated with the processor by calculating, based on the...
7363442 Separate handling of read and write of read-modify-write  
A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows...
7363440 System and method for dynamically accessing memory while under normal functional operating conditions  
A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a...
7363419 Method and system for terminating write commands in a hub-based memory system  
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub....
7363399 Method, apparatus and computer program product providing storage network dynamic tuning of I/O flow with Queue Depth  
In accordance with a computer program product, apparatus and a method there is provided a redundant network wherein a host computer operates with a plurality of storage devices by monitoring...
7360050 Integrated circuit memory device having delayed write capability  
An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the...
7360036 Data memory circuit  
A data memory circuit is provided. In one embodiment, the data memory circuit comprises a plurality of addressable memory cells, a command decoding device for decoding external commands and a...
7360012 Semiconductor memory device including memory controller for transmitting writing rate information to memory access device  
A semiconductor memory card 1 includes a user data area 21 and a management information area 22 , in a data storing unit 2 . According to a writing test command from a memory access device 6...
7356632 Data memory controller that supports data bus invert  
The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a...
7356631 Apparatus and method for scheduling requests to source device in a memory access system  
An apparatus and method for scheduling requests to a source device is provided. The apparatus comprises a high-priority request queue for storing a plurality of high-priority requests to the source...
7353357 Apparatus and method for pipelined memory operations  
A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus...
7353356 High speed, low current consumption FIFO circuit  
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
7350051 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream  
A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of...
7350045 Dynamic memory heap tagging  
A data structure within a block of allocable memory of a memory structure such as a heap is used to identify the function that is responsible for causing memory problems such as random overwrites,...
7350025 System and method for improved collection of software application profile data for performance optimization  
The present invention is directed to a system and method for improved collection of application profile data for performance optimization. The invention provides a mechanism for storing usage bits...
7350022 Storage system and storage control method with a password for device management  
In a storage system, which includes a storage device and a disk control device that controls data transfer between the storage device and a host computer, a security of storage medium making up the...
7346752 Memory controller and image forming device provided with the same  
In order to output an active command to an SDRAM, at time t 0 , output of a valid row address starts and a control signal ras# enters the active state. Thereafter, a control signal cs# enters the...
7345933 Qualified data strobe signal for double data rate memory controller module  
A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that...
7345901 Computer system having daisy chained self timed memory chips  
A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command...
7343463 Data storage unit, executable command selection method, and data processing method  
An executable command selection system and method are provided. A command is selected as the next-to-be-executed command when the execution waiting time for the command is less than or equal to a...
7343457 Dual active bank memory controller  
A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a...
7340584 Sequential nibble burst ordering for data  
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode...
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