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7634623 |
Method and apparatus for self-timed data ordering for multi-data rate memories and system incorporating same
A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory...
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7634630 |
Storing authentication information in a content unit on an object addressable storage system
Aspects of the invention relate to sharing content stored on an object addressable storage (OAS) system among a plurality of users of the OAS system and authenticating users to an OAS system. In...
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7617358 |
Methods and structure for writing lead-in sequences for head stability in a dynamically mapped mass storage device
Methods and structures for writing thermal lead-in sequences to provide head stability in a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied...
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7617368 |
Memory interface with independent arbitration of precharge, activate, and read/write
A memory interface coupling a plurality of clients to a memory having memory banks provides independent arbitration of activate decisions and read/write decisions. In one implementation, precharge...
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7617352 |
Memory controller, flash memory system having memory controller and method for controlling flash memory device
A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target...
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7610458 |
Data processing system, processor and method of data processing that support memory access according to diverse memory models
A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store...
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7606983 |
Sequential ordering of transactions in digital systems with multiple requestors
A digital system with an improved transaction ordering policy is disclosed. Individual occurrences of requests for access to common system resources specify whether or not the request is ordered....
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7606944 |
Dynamic input/output optimization within a storage controller
A system and method for optimizing accesses to storage devices based on RAID I/O request characteristics is disclosed. A current I/O request processed by a storage controller is analyzed for...
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7603533 |
System and method for data protection on a storage medium
A method of and system for protecting a disk drive or other data storage includes mounting a virtual storage that combines a full access temporary storage and a READ-only portion of a main storage,...
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7603527 |
Resolving false dependencies of speculative load instructions
Methods and apparatus for resolving false dependencies associated with speculatively executing load instructions in a processor core are described. In one embodiment, physical addresses of a load...
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7594089 |
Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of...
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7584229 |
Method and system for priority-based allocation in a storage pool
A method for priority-based allocation in a storage pool involves receiving a request to write a data item in the storage pool, where the storage pool includes multiple metaslabs, and where each of...
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7584321 |
Memory address and datapath multiplexing
Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed...
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7577814 |
Firmware memory management
A firmware memory manager allocates memory for code and data based on a lifespan associated with each allocation. The memory manager determines whether each allocated block of memory is needed only...
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7577690 |
Managing checkpoint queues in a multiple node system
Techniques are provided for managing caches in a system with multiple caches that may contain different copies of the same data item. Specifically, techniques are provided for coordinating the...
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7574573 |
Reactive placement controller for interfacing with banked memory storage
An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a...
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7573484 |
Image processing apparatus and controlling method therefor
An image processing apparatus for managing a memory device having a plurality of storage areas including a storage area storing out-of-use information and a free area storing no information, the...
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7571296 |
Memory controller-adaptive 1T/2T timing control
Circuits, methods, and apparatus that adaptively control 1 T and 2 T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as...
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7565498 |
System and method for maintaining write order fidelity in a distributed environment
Various systems and methods for maintaining write order fidelity in a distributed environment are disclosed. One method, which can be performed by each node in a cluster, involves associating a...
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7565497 |
Coarse write barrier control mechanism
A method for a coarse write barrier control mechanism comprises maintaining a control table comprising a plurality of entries, where each entry may include an encoding of a write barrier function...
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7562196 |
Method and apparatus for determining precedence in a classification engine
A precedence determination system including a first type memory bank configured to receive a first search signal and to provide first search result indications, a second type memory bank configured...
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7562194 |
Method and apparatus for exploiting parallelism across multiple traffic streams through a single channel
Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the...
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7558923 |
Prevention of live-lock in a multi-processor system
Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and...
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7555613 |
Storage access prioritization using a data storage device
Herein described is a method and system of prioritizing access to data stored in one or more data processing devices communicatively coupled to the data storage device. The method may be based on...
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7552301 |
Information processing apparatus and memory access arranging method
An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control...
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7546425 |
Data processor with a built-in memory
A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect...
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7543132 |
Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data...
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7543122 |
System and method for obscuring hand-held device data traffic information
Increasing security for a hand-held data processing device with communication functionality where such a device includes an access-ordered memory cache relating to communications carried out by the...
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7529830 |
Storage system and communication control method
A storage system includes: a protocol control unit that processes a file access request from a NAS client; and a priority calculation unit that calculates a priority set for the reply packet...
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7529895 |
Method for prefetching non-contiguous data structures
A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an...
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7529896 |
Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules
A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first...
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7526606 |
High-speed redundant disk controller methods and systems
Various apparatus and methods for controlling data for a redundant array of inexpensive/independent disks (RAID) are presented. For example, in one illustrative embodiment, a controlling apparatus...
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7526628 |
Optimizing cache efficiency within application software
The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and...
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7523157 |
Managing a plurality of processors as devices
Managing a computer system's multiple processors as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a...
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7523266 |
Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level
One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor....
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7519744 |
Method and apparatus for managing I/O paths on a storage network using priority
A processing apparatus which stores a first information piece about attributes identifying a specific process generating data input/output requests in such a manner that the first information piece...
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7516295 |
Method of remapping flash memory
A method of re-mapping a flash memory, which minimizes the number of times the flash memory, is accessed and helps to evenly use the entire area of the flash memory, is provided. The method...
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7512743 |
Using shared memory with an execute-in-place processor and a co-processor
The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be...
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7512753 |
Disk array control apparatus and method
A disk array control apparatus determines-whether or not a I/O process request from a host computer is causing a cache hit at a disk cache memory. The apparatus identifies the I/O process request...
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7512754 |
System and method for optimizing storage utilization
In a storage area network, the storage pool is the principal component that determines the storage quality of service in the network. The proposed system's goal is to balance the utilizations of...
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7506104 |
Packet processor memory interface with speculative memory reads
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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7506126 |
Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals,...
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7506114 |
Data transfer device which executes DMA transfer, semiconductor integrated circuit device and data transfer method
A data transfer device which controls data transfer between a first memory device and a second memory device, includes a first transfer arbiter circuit and a second transfer arbiter circuit. The...
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7496721 |
Packet processor memory interface with late order binding
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the...
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7496722 |
Memory mapped page priorities
A method of communicating memory mapped page priorities includes a software application storing page priority information for a memory mapped file on a computer readable medium, and an operating...
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7486688 |
Compact packet switching node storage architecture employing Double Data Rate Synchronous Dynamic RAM
A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal...
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7487304 |
Packet processor memory interface with active packet list
A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which...
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7487314 |
Restricting memory access to protect data when sharing a common address space
A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For...
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7487305 |
Prioritized bus request scheduling mechanism for processing devices
A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The...
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7478209 |
Packet processor memory interface with conflict detection and checkpoint repair
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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