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9032167 Write operations to and from multiple buffers  
Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for...
9009409 Cache region concept  
A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a...
9009397 Storage processor managing solid state disk array  
A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and...
9009436 Flushed data alignment with physical structures  
A method and system are disclosed herein for performing operations on a parallel programming unit in a memory system. The parallel programming unit includes multiple physical structures (such as...
8966164 Storage processor managing NVME logically addressed solid state disk array  
A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and...
8959297 Retrieving a user data set from multiple memories  
An apparatus and associated methodology for a data storage system having a data storage space operably transferring user data via input/output (I/O) commands between the data storage system and...
8959298 System and method for managing performance of a computing device having dissimilar memory types  
Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory...
8954657 Storage processor managing solid state disk array  
A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and...
8949554 Idle power control in multi-display systems  
A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for...
8938583 System and method for concurrently executing data access requests  
Embodiments of the invention are directed to systems and methods for optimizing data access request handling in a non-volatile memory (NVM) device. In one embodiment, the device may include a...
8935489 Adaptively time-multiplexing memory references from multiple processor cores  
The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine...
8924660 Split-word memory  
Method, process, and apparatus to efficiently store, read, and/or process portions of word data. A portion of a data word, which includes multiple portions, may be read by a computer processor....
8904095 Data storage device and operating method thereof  
An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical...
8892845 Segmenting data for storage in a dispersed storage network  
A method begins by a processing module receiving data of a file for storage in a dispersed storage network (DSN) memory and determining a segmentation scheme for storing the data. The method...
8892829 Methods, systems, and computer readable media for integrated sub-block interleaving and rate matching  
Methods, systems, and computer readable media for fast, reduced memory and integrated sub-block interleaving and rate matching are disclosed. According to one aspect, the subject matter described...
8886898 Efficient interleaving between a non-power-of-two number of entities  
Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system...
8886897 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips  
A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the...
8880818 Reconfigurable memory controller  
Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an...
8878860 Accessing memory using multi-tiling  
An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals....
8880812 WWN table management systems and methods  
A serial attached small computer systems interface (SAS) module includes a first port with (i) a first physical layer device and (ii) a first port control module. The first physical layer device...
8874858 Reconfigurable interleaver having reconfigurable counters  
A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver...
8874837 Embedded memory and dedicated processor structure within an integrated circuit  
An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random...
8850100 Interleaving codeword portions between multiple planes and/or dies of a flash memory device  
A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a...
8850600 Data storage device and data storage system including the same  
A data storage device protecting security code stored therein and a data storage system including same are disclosed. The data storage device efficiently prevents unauthorized access to the...
8819359 Hybrid interleaving in memory modules by interleaving physical addresses for a page across ranks in a memory module  
A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses...
8817033 Method and apparatus for performing adaptive memory bank addressing  
A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component...
8806103 System and method for interleaving memory  
One system may comprise an interleave system that determines a desired interleave for at least a selected portion of a distributed memory system. A migration system is associated with the...
8799607 Memory controller and method for accessing a plurality of non-volatile memory arrays  
A memory controller (16) is used in a system (10) having a main memory (22) and a set of non-volatile memories (26, 32, 38, 44). Each non-volatile memory comprises a plurality of sectors (S0-S28),...
8799593 Flash memory devices, data randomizing methods of the same, memory systems including the same  
Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at...
8793445 Method and system for improved deskewing of data  
Embodiments of the present invention are directed to a method, computer-readable medium and system for deskewing data. More specifically, skewed data is accessed and written into a plurality of...
8782356 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions  
Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a...
8775750 Interleaver with parallel address queue arbitration dependent on which queues are empty  
An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an...
8769219 Disk controller configured to perform out of order execution of write operations  
A storage controller including a processor and a memory controller. The processor is configured to generate a command corresponding to a first write operation and a second write operation, in...
8751769 Efficient address generation for pruned interleavers and de-interleavers  
Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a...
8725943 Method and system for secure data storage  
A method and system for secure data storage and retrieval is provided. A sequence of data units is divided into multiple subsets of data units corresponding to multiple data channels. The multiple...
8719505 Method for increasing cache size  
A method for increasing storage space in a system containing a block data storage device, a memory, and a processor is provided. Generally, the processor is configured by the memory to tag...
8719519 Split-word memory  
Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor....
8713242 Control method and allocation structure for flash memory device  
A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the...
RE44848 Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter  
An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation...
8683070 Stream identifier hash table  
A system may route media stream samples in time-stamped packets to a media interface. The system may determine a hash value from a stream identifier that identifies a source media stream...
8681560 Circuit for the optimization of the programming of a flash memory  
A memory device includes a plurality of memory cells and programming circuitry configured to select a group of memory cells, receive a first data word and program memory cells of the selected...
8683149 Reconfigurable memory controller  
Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an...
8671254 Processes, circuits, devices, and systems for concurrent dual memory access in encryption and decryption  
A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and...
8659778 Image forming apparatus operable in first and second modes for processing job data, and job data storing method  
An image forming apparatus including: a storage device composed of a plurality of storage sections for storing a job data to be input; an image forming section for performing an image formation...
8639894 Efficient read and write operations  
Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for...
8626988 System and method for uncoded bit error rate equalization via interleaving  
A device, method, and computer readable medium for programming a codeword are presented. The method includes writing a first codeword portion to portions of nonvolatile memory rows, and writing a...
8627037 Memory system having nonvolatile semiconductor storage devices  
According to an embodiment, a memory system includes a memory unit, a memory controller, a timer and a timer control unit. The memory unit has nonvolatile first and second chips capable of holding...
8627022 Contention free parallel access system and a method for contention free parallel access to a group of memory banks  
A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K...
8621164 Tiered storage pool management and control for loosely coupled multiple storage environment  
A system comprises a first storage system including a first storage controller, which receives input/output commands from host computers and provides first storage volumes to the host computers;...
8612672 Adaptive physical allocation in solid-state drives  
A solid-state drive, a solid-state drive access unit allocation/data storage approach, and a solid-state drive access unit access/data retrieval approach are described that improve the efficiency...