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7627712 |
Method and system for managing multi-plane memory devices
A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual...
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7620784 |
High speed nonvolatile memory device using parallel writing among a plurality of interfaces
Described is a high speed nonvolatile memory device and technology that includes a controller coupled via interfaces to sets of nonvolatile storage, such as separate flash memory chips or separate...
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7620710 |
System and method for performing multi-path storage operations
Systems and methods for allocating transmission resources within a computer network are provided. In some embodiments of the invention, communication links may be assigned based on predefined...
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7617367 |
Memory system including a two-on-one link memory subsystem interconnection
A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a...
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7613866 |
Method for controlling access to a multibank memory
The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording...
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7610457 |
Interleaving method and system
An interleaving method employing symbol interleaving, tone interleaving, and cyclic interleaving for transmitting data includes storing data at write address values in a memory which are...
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7603512 |
Dynamic memory refresh controller, memory system including the same and method of controlling refresh of dynamic memory
A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a...
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7602512 |
Method and apparatus for authentication in secure printing
Secrecy of printed matter is raised and charges for a storing area are more accurately charged. According to the invention, a printing apparatus is instructed so as to store print data...
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7579683 |
Memory interface optimized for stacked configurations
A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that...
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7574548 |
Dynamic data transfer control method and apparatus for shared SMP computer systems
As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there...
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7555595 |
Methods and apparatus for writing servo frames to and/or verifying data areas of a storage medium
Methods and apparatus are disclosed for writing and verifying servo frames written on a storage medium, for verifying data areas of a storage medium, and for writing and verifying servo frames and...
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7552294 |
System and method for processing multiple concurrent extended copy commands to a single destination device
Embodiments of the present invention provide systems and methods for processing concurrent extended copy commands. One embodiment can include a method for processing multiple extended copy commands...
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7552292 |
Method of memory space configuration
A method is disclosed for utilizing at least one bit within the logical address code of a memory unit formed by Dynamic Random Access Memory (DRAM) to be the control code for interleaving the...
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7543121 |
Computer system allowing any computer to copy any storage area within a storage system
A computer system having a plurality of host computers and a storage system is provided which allows any one host computer to perform a global copy operation on any arbitrary or all storage areas...
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7536530 |
Method and apparatus for determining a dynamic random access memory page management implementation
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the...
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7536520 |
Method and apparatus for native method invocation and changing memory bank
A method and apparatus for native method invocation and changing memory bank. A method return frame of a smart card stores the status of a native method invocation, and a memory bank flag points a...
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7523288 |
Dynamic fragment mapping
A dataset is divided into pieces and stored at multiple locations and the system dynamically increases or decreases the number of storage locations where the pieces of the data set may be stored. A...
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7519781 |
Physically-based page characterization data
Circuits, methods, and apparatus for efficiently storing page characteristics. Page characteristics for memory pages are stored post address translation using addresses for physical locations in...
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7506126 |
Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals,...
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7493463 |
Code size reduction method through multiple load/store instructions
A method to transfer a plurality of data stored in a memory using one instruction. In a memory including at least two regions to which the addresses are assigned respectively, data are allocated to...
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7493457 |
States encoding in multi-bit flash cells for optimizing error rate
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same...
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7490282 |
Method and apparatus of turbo encoder
Briefly, an apparatus, a method and a wireless communication device are provided. The wireless communication device includes a turbo encoder to generate an encoded data block and a transmitter to...
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7484069 |
Watchpointing unaligned data accesses
A data processing system incorporating watchpoint registers is provided. The memory accesses to be detected may be unaligned memory accesses. The watchpoint may operate in a normal mode and also in...
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7469365 |
Method and device for interleaving and method and device for de-interleaving
The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit...
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7469318 |
System bus structure for large L2 cache array topology with different latency domains
A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock...
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7468994 |
Method and apparatus for interleave processing, and computer program product for interleave processing
An apparatus defines interleave-processing segments to be interleaved in a backward direction relative to a flow direction of bit streams. The segments are defined every time the segments, ILVU-BR,...
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7461218 |
Size-based interleaving in a packet-based link
A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a...
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7461216 |
Memory controller
A memory controller for accessing a memory module comprising a plurality of memory banks. The memory controller is operable to write copies of program data to one or more memory banks according to...
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7447848 |
Memory device row and/or column access efficiency
Embodiments for retrieving data from memory devices using sub-partitioned addresses are disclosed.
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7444460 |
Data storage device, method for updating management information in data storage device, and computer program
The invention provides a data storage device and a method of updating management information, capable of dealing with management information in a highly reliable manner so that information is not...
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7433429 |
De-interleaver method and system
In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer.
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7423981 |
Method and apparatus for an incremental update of a longest prefix match lookup table
A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is...
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7418571 |
Memory interleaving
Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.
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7415584 |
Interleaving input sequences to memory
An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while...
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7404036 |
Rebalancing of striped disk data
Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second set...
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7398362 |
Programmable interleaving in multiple-bank memories
A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank...
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7394412 |
Unified interleaver/de-interleaver
An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the...
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7386691 |
Electronic device for reducing interleaving write access conflicts in optimized concurrent interleaving architecture for high throughput turbo decoding
An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having...
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7373453 |
Method and apparatus of interleaving memory bank in multi-layer bus system
A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating...
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7370252 |
Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter
An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation...
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7369135 |
Memory management system having a forward progress bit
A virtual memory system that maintains a list of pages that are required to be resident in a frame buffer to guarantee the eventual forward progress of a graphics application context running on a...
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7360040 |
Interleaver for iterative decoder
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO)...
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7346750 |
Memory interleave system
A memory interleave system includes M (M=2 p , where p is a natural number) memory banks, M memory control units (MCU) corresponding respectively to the M memory banks, N (a natural number) CPUs,...
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7340664 |
Single engine turbo decoder with single frame size buffer for interleaving/deinterleaving
A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the...
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7318115 |
IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic
Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed...
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7318114 |
System and method for dynamic memory interleaving and de-interleaving
In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each...
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7296124 |
Memory interface supporting multi-stream operation
A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data...
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7296112 |
High bandwidth memory management using multi-bank DRAM devices
The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet...
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7290109 |
Memory system and memory card
A memory system includes a plurality of nonvolatile memory chips (CHP 1 and CHP 2 ) each having a plurality of memory banks (BNK 1 and BNK 2 ) which can perform a memory operation independent of...
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7290099 |
Using parallelism for clear status track processing during error handling behavior in a storage system
Tracks of meta data are cleared in a storage server by allocating task control blocks for executing associated tasks in parallel. Throttling and recycling of task control blocks is provided to...
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