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6412039 Cross-bank, cross-page data accessing and controlling system  
A cross memory bank, cross memory page data accessing and controlling unit that provides more efficient transfer of data between a CPU and a memory cluster is described. The data accessing and...
6408367 Data path architecture and arbitration scheme for providing access to a shared system resource  
A system interconnect architecture and associated arbitration scheme that provides for the interleaving of multiple accesses to a shared system resource by multiple system components on a data...
6405293 Selectively accessible memory banks for operating in alternately reading or writing modes of operation  
Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while...
6405286 Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes  
A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to...
6401177 Memory system for restructuring a main memory unit in a general-purpose computer  
A memory system has a plurality of memory banks, performs interleaving between the memory banks, and structures a memory by dividing into a plurality of memory blocks which are independently...
6389520 Method for controlling out of order accessing to a multibank memory  
A method is described for interleaving bank and page access to a multibank memory device, such as an SDRAM or SLDRAM. An address detector detects a pending page access, and the associated data...
6389514 Method and computer system for speculatively closing pages in memory  
The present invention provides a method and an apparatus for addressing a main memory unit in a computer system which results in improved page hit rate and reduced memory latency by only keeping...
6381668 Address mapping for system memory  
For optimizing access to system memory having a plurality of memory banks, interleaving can be used when storing data so that data sequences are distributed over memory banks. The invention...
6378065 Apparatus with context switching capability  
The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a...
6360305 Method and apparatus for optimizing memory performance with opportunistic pre-charging  
A memory controller for a dynamic random access memory which pre-charges active banks in a particular chip select when an eight quadword access is made to another bank within that same chip...
6356988 Memory access system, address converter, and address conversion method capable of reducing a memory access time  
On storing two-dimensional arrangement data into a memory (1) having banks, 2n in number, each of which is individually assigned with a bank number B and includes row addresses identified by row...
6356991 Programmable address translation system  
A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs...
6356986 Method and apparatus for analyzing a main memory configuration  
A method and apparatus for analyzing the configuration of a computer main memory. A complex memory controller, which imposes restrictions on the memory's configuration, determines whether a...
6343335 System for repositioning an I/O device to a predetermined position to retry a program without knowledge of which part of the program caused the retry  
Repositioning within an input/output device is accomplished without any knowledge of where the input/output device is currently positioned. The input/output device is repositioned to a...
6341330 Method and system for caching a selected viewing angle in a DVD environment  
A caching method and system for use in a DVD player is disclosed that selectively caches only one of multiple viewing angles recorded on the DVD medium. This system allows optimization of the...
6341326 Method and apparatus for data capture using latches, delays, parallelism, and synchronization  
A static random access memory device used in a system having a data clock includes a recirculating counter producing a pair of clocking signals and n data latches each connected to a source of...
6339799 Method of repositioning an I/O device to a predetermined position to retry a program without knowledge of which part of the program caused the retry  
Repositioning within an input/output device is accomplished without any knowledge of where the input/output device is currently positioned. The input/output device is repositioned to a...
6334159 Method and apparatus for scheduling requests within a data processing system  
A method and apparatus for scheduling the execution of selected requests received in a first-in-time sequence, such that two or more request types are executed in a particular sequence for...
6330585 Transfer information using optical fiber connections  
This invention relates to concept of transferring information in a program storage device and a computer program device readable by a digital processing apparatus and a program means on the...
6321311 Interleave read address generator  
An interleave read address generator of an interleaver for use in a CDMA mobile communication terminal. The interleave read address generator includes a base-18 counter for counting a clock input...
6317857 System and method for utilizing checksums to recover data  
A system for storing and retrieving data utilizes a plurality of memory units having memory locations for storing data values. A checksum of a plurality of the data values in a particular checksum...
6292867 Data processing system  
A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for...
6266733 Two-level mini-block storage system for volume data sets  
A two-level skewing architecture is imposed on the memory subsystem of a volume rendering system in which voxel data is stored in mini-blocks assigned to a set of DRAM memory modules, thereby...
6260122 Memory device  
Nine memories (10a.about.10i) are provided, out of which five memories are made memories for the present processing. Meanwhile, the remaining four memories are made memories for receiving and...
6256717 Data access controller and data access control method  
A data access controller has its SRAM adapted to hold two ECC blocks so that the SRAM is used efficiently for multiple kinds of processes. At playback of data, writing of ECC block A from the...
6249827 Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines  
A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively...
6247104 Memory access control circuit  
Disclosed is a memory access control circuit for conducting the interleave control that, between an access request and a data transfer for the access request, another access request and data...
6243797 Multiplexed semiconductor data transfer arrangement with timing signal generator  
A multiplexing arrangement for transferring data retrieved from a memory array to data outputs of a semiconductor memory, including a multiplexing circuit that is responsive to latency select...
6233655 Method for Quad-word Storing into 2-way interleaved L1 cache  
A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and...
6233662 Method and apparatus for interleaving memory across computer memory banks  
The present invention advantageously optimizes the flexibility built into some interleavers by novelly configuring an interleaver to improve the throughput of access to computer memory by...
6226720 Method for optimally configuring memory in a mixed interleave system  
Memory bank pairs are sorted utilizing variables determined by a scoring criteria. The scores for the variables are based on the number of memory blocks in a memory bank that are filled; the total...
6226707 System and method for arranging, accessing and distributing data to achieve zero cycle penalty for access crossing a cache line  
A data processing system and method for arranging and accessing information that crosses cache lines utilize dual cache columns. The dual cache columns are formed of two access-related cache...
6202120 System and method for accessing data between a host bus and a system memory bus where the system memory bus has a data path that is twice the width of the data path for the host bus  
A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory...
6202133 Method of processing memory transactions in a computer system having dual system memories and memory controllers  
A method of operating a computer system having first and second random access memory (RAM) modules for storing digital information, and first and second system controllers coupled to the first and...
6195726 Method and apparatus for performing patterned read and write operations  
A read/write drive such as a DVD+RW drive performs interleaved read and write operations on a recordable medium without relying on long seeks. During a first mode of operation, the read/write...
6185654 Phantom resource memory address mapping system  
A phantom-resource memory address mapping system reduces access latency in a memory configured as a stacked-hybrid or filly-interleaved hierarchy of memory resources. The address mapping system...
6178530 Addressing scheme for convolutional interleaver/de-interleaver  
A memory addressing scheme suitable for use for either interleaving or de-interleaving data bytes of, e.g., a broadcast digital television (DTV) data stream. A number of memory branches are...
6175901 Method for initializing and reprogramming a control operation feature of a memory device  
A method for programming a synchronous dynamic random access memory (SDRAM) device including a memory array is disclosed. In the method, the SDRAM device is initially programmed to have a first...
6151690 Interleaving and de-interleaving method for digital data, interleaving and de-interleaving devices, and communication system  
A triangular interleaver (INTERLEAVER) contains a triangular shaped matrix (MAT) of memory cells, each row of which constitutes a first-in-first-out queue. To increase or decrease the interleave...
6151665 Method and apparatus for mirroring blocks of information in a disc drive storage system  
A method and apparatus for managing blocks of information in a disc drive storage system. One embodiment is directed to a disc drive storage system that employs a plurality of disc drives, and...
6145063 Memory system and information processing system  
In a memory composed of a plurality of banks, even if succeeding access is performed to the same bank as that being currently accessed, the succeeding access can be controlled according to the...
6138214 Synchronous dynamic random access memory architecture for sequential burst mode  
An electronic memory device which includes a memory array having a plurality of memory cells arranged into a plurality of units. Each unit is divided into a first portion including only even...
6131146 Interleave memory control apparatus and method  
A high multiplexing degree or interleaving factor is achieved in a memory having banks of different capacities. A group judging circuit generates the relevant interleave group and addresses in...
6125432 Image process apparatus having a storage device with a plurality of banks storing pixel data, and capable of precharging one bank while writing to another bank  
Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically...
6115781 Method and system for storage and retrieval of data on a tape medium  
A general purpose method is provided for interfacing with a storage device having a tape medium. The method includes receiving data from a first source, and creating a first data packet having at...
6112200 Interleaving of data types in a geographic database and methods for application  
A geographic database for use with a navigation application program that provides navigation features to an end-user. The geographic database includes a plurality of data records of a first type...
6108699 System and method for modifying membership in a clustered distributed computer system and updating system configuration  
Multiple nodes can concurrently gain membership in a cluster of nodes of a distributed computer system by broadcasting reconfiguration messages to all nodes of the distributed computer system. In...
6108745 Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes  
An address routing scheme supports a variety of memory sizes and interleaving schemes. In one embodiment, any address bit provided by the processor can be routed to any bank, row, or column bit,...
6108693 System and method of data communication in multiprocessor system  
A multiprocessor system has a transmitting processor and a receiving processor. In response to a transmission request, the transmitting processor implements means for selecting one of two...
6108371 System and method for writing mixed interleaved and non-interleaved data to a modem register  
A modem having an interactive clearing circuit that provides the facility for the modem to mix interleaved and non-interleaved writes to a FIFO without timing problems or data transfer problems...