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6754765 Flash memory controller with updateable microcode  
A flash memory controller with a volatile program and data memory is disclosed. The controller loads microcode and data into the program and data memory from a flash memory array upon powerup of...
6754790 Method of accessing memory of de-interleaving unit  
A method is proposed for accessing the memory of a de-interleaving unit. The conventional access method has the drawback of ineffective use of the memory space of the de-interleaving unit, while...
6751692 Adapter for memory device and connecting method using the same  
An adapter for a memory device for connecting a detachable memory device to an AT attachment (ATA) interface of a host computer and a connecting method using the adapter are presented. With a...
6748505 Efficient system bus architecture for memory and register transfers  
A method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines...
6748033 De-interleave circuit  
To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator (3) supplies address data (A) to a...
6748561 Interleavers and de-interleavers  
A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved...
6745279 Memory controller  
A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined...
6745277 Intelligent interleaving scheme for multibank memory  
A network processing device intelligently interleaves packets for read and write access requests in a multibank memory. The system intelligently writes packets into the different memory banks so...
6741256 Predictive optimizer for DRAM memory  
A predictive optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit maintains a queue of pending requests for data from the...
6738880 Buffer for varying data access speed and system applying the same  
A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be...
6738874 Controller architecture and strategy for small discontiguous accesses to high-density memory devices  
A RAM device including a memory and a memory controller. The memory controller can be configured to buffer incoming requests, prioritize the requests into a final order, and submit the requests to...
6728826 Semiconductor storage device in which commands are sequentially fed to a plurality of flash memories to continuously write data  
A semiconductor storage apparatus such as a disk pack in which a controller sends a second write command or instruction while a write operation for a first write command or instruction is being...
6721858 Parallel implementation of protocol engines based on memory partitioning  
A method and system for the parallel implementation of protocol engines based on memory partitioning. The method comprises the steps of partitioning a shared memory space into multiple...
6708260 Managing data in a queue  
The present invention, in various embodiments, provides techniques for managing data in a queue. In one embodiment, two write pointers control writing into a memory queue and one read pointer...
6704848 Apparatus for controlling time deinterleaver memory for digital audio broadcasting  
An apparatus and method are provided for controlling a time deinterleaver for digital audio broadcasting (DAB) that reduces a required minimum memory capacity of a DAB receiver. The method and...
6701419 Interlaced memory device with random or sequential access  
A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock...
6665768 Table look-up operation for SIMD processors with interleaved memory systems  
An apparatus and method for accessing data in a processing system are described. The system includes multiple processing elements for executing program instructions. The processing system can be a...
6654860 Method and apparatus for removing speculative memory accesses from a memory access queue for issuance to memory or discarding  
A memory controller generates speculative and non-speculative memory access requests. Several approaches are used to prevent speculative memory access requests from interfering with...
6651138 Hot-plug memory catridge power control logic  
A hot-pluggable memory cartridge for use in a redundant memory system. More specifically, the control logic and method for implementing a plurality of memory cartridges which may be hot-plugged...
6640295 Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions  
In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory...
6629219 Method and apparatus for providing highly programmable memory mapping and improved interleaving  
A method and apparatus for providing highly programmable memory mapping and improved interleaving includes a system address chip that maps a received memory transaction address to an intermediate...
6625706 ATD generation in a synchronous memory  
A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for...
6622213 Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions  
A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit....
6622218 Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system  
The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal...
6622217 Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system  
The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal...
6611894 Data retrieval apparatus  
The present invention relates to a data retrieval apparatus for retrieving the data from a number of places of data stored in memories which adopts binary search method and enables high-speed...
6604166 Memory architecture for parallel data access along any given dimension of an n-dimensional rectangular data array  
A memory architecture is provided to enable parallel access along any dimension of an n-dimensional data array. To enable parallel access of s data elements along any dimension, the data elements...
6598198 Deinterleaving device that releases a plurality of types of interleaving simultaneously  
The deinterleaving device of this invention deinterleaves an input transmission frame and outputs the deinterleaved frame, the transmission frame being obtained by performing inter-frame...
6587913 Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode  
A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a...
6584542 Microwave paging architecture  
A Time Division Multiple Access (TDMA) mobile station architecture consuming less power and random access memory (RAM) is presented herein. The mobile station includes a coprocessor which executes...
6567900 Efficient address interleaving with simultaneous multiple locality options  
A computer system includes multiple processors, each of which includes an associated memory. Each of the processors is capable of accessing the memory of all other processors. Memory can be stored...
6567901 Read around speculative load  
A processor of a system initiates memory read transactions on a bus and provides information regarding the speculative nature of the transaction. A bus device, such as a memory controller, then...
6564284 Apparatus for controlling a multibank memory device  
An apparatus is described for interleaving bank and page access to a multibank memory device, such as an SDRAM or SLDRAM. An address detector detects a pending page access, and the associated data...
6564304 Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching  
A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access...
6557071 Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage  
A memory subsystem for a computer system includes a memory controller that has a data strobe generator. The memory subsystem further includes a Dynamic Random Access Memory (“DRAM”) array coupled...
6553478 Computer memory access  
A memory for a computer system that includes a plurality of memory banks which provide an interleaved memory region as well as X and Y memory regions. Each memory access address includes a most...
6553450 Buffer to multiply memory interface  
Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory...
6549974 Semiconductor storage apparatus including a controller for sending first and second write commands to different nonvolatile memories in a parallel or time overlapped manner  
A semiconductor storage apparatus including a controller which writes data into different nonvolatile semiconductor memories in a parallel or timed overlapped manner. The controller, responsive to...
6523080 Shared bus non-sequential data ordering method and apparatus  
A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified...
6507850 Segment aggregation and interleaving of data types in a geographic database and methods for use thereof in a navigation application  
A geographic database for use with a navigation application program that provides navigation features to an end-user. The geographic database includes a plurality of data records of a first type...
6496910 Method and device for loading instruction codes to a memory and linking said instruction codes  
A method for loading instruction codes to a first memory and linking said instruction codes is proposed, whereby at least one instruction code has as parameter an address which during a loading...
6487140 Circuit for managing the transfer of data streams from a plurality of sources within a system  
A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with...
6480943 Memory address interleaving and offset bits for cell interleaving of memory  
A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into...
6470431 Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data  
An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of...
6467015 High speed bus interface for non-volatile integrated circuit memory supporting continuous transfer  
A memory system with non-volatile integrated circuit memory devices including an interface for a high speed bus is described, supporting continuous writes at the bus speed, without the possibility...
6463503 Method and system for increasing concurrency during staging and destaging in a log structured array  
Aspects for increasing concurrency during staging and destaging of a log structured array (LSA) are described. In an exemplary method aspect, the method includes determining a process type making...
6453380 Address mapping for configurable memory system  
In a system in which data are stored in an interleaved fashion in a memory consisting of a plurality of memory banks, a method and means are provided for mapping a given address into a memory bank...
6453358 Network switching device with concurrent key lookups  
A switching device for forwarding network traffic to a desired destination on a network, such as a telephone or computer network. The switching device includes multiple ports and uses a lookup...
6449064 Method and apparatus for image formation that can handle simultaneously input data without causing a delay  
An image forming apparatus includes a plurality of memory devices, each including at least one image memory which stores image data. A controller controls input and output operations for the image...
6446158 Memory system using FET switches to select memory banks  
A computer memory system provides a double data rate (DDR) memory output while requiring memory chips with only half the frequency limit of the prior art DDR memory chips. The system contains a...