Match Document Document Title
7038691 Two-dimensional buffer pages using memory bank alternation  
Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations. In one implementation, a buffer page system includes: a data source, providing data elements in a...
7039762 Parallel cache interleave accesses with address-sliced directories  
A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the...
7035986 System and method for simultaneous access of the same line in cache storage  
An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced...
7027798 Electronic terminal having an emergency message function and insurance system using the same  
An electronic terminal having an emergency message function which can be easily used little inducing erroneous operation or operation out of fun. The electronic terminal comprises a predetermined...
7020736 Method and apparatus for sharing memory space across mutliple processing units  
A method and apparatus for sharing memory space of multiple memory units by multiple processing units are described. In an embodiment, a method includes storing a set of data across more than one...
7017010 Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length  
The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated...
7010652 Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency  
A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and...
6996686 Memory subsystem including memory modules having multiple banks  
A memory subsystem including memory modules having multiple banks. A memory subsystem includes a memory controller and a plurality of memory modules. The plurality of memory modules may be coupled...
6993625 Load balancing storage system  
A disk storage subsystem allocating an equivalent number of hard disk drives to each loop, alternately connecting the connecting bays of hard disk drives to optical fiber channels provided with...
6990556 System and method for simultaneous access of the same doubleword in cache storage  
An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced...
6988170 Scalable architecture based on single-chip multiprocessing  
A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory...
6987470 Method to efficiently generate the row and column index for half rate interleaver in GSM  
A method and apparatus for interleaving bits in a first sequence is disclosed. An exemplary method comprises storing a set of offset values in at least one table, applying in order each of the set...
6986000 Interleaving apparatus and deinterleaving apparatus  
A signal record reproduction device 1 of the invention comprises a microcomputer 12 and a memory 17. A series of data blocks are divided into a plurality of items of element data. The element data...
6981095 Hot replace power control sequence logic  
The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control...
6976138 Semiconductor device for data communication control and radio communication apparatus  
The required RAM capacity is reduced by dividing an interleaving RAM in a baseband modulator into a plurality of areas and having the read side and the write side use some common areas on a...
6957310 Interleave address generation device and interleave address generation method  
Counter control section 101 increments a row number and column number on a two-dimensional array for a block interleave expressed by a matrix two-dimensional array, outputs the incremented numbers...
6944729 Multiplexing-interleaving and demultiplexing-deinterleaving  
The processor (24) retrieves from a memory (22) values of a signal recovered from received wireless signal and demultiplexes and de-interleaves them simultaneously. The system can be operated in...
6944748 Signal processor executing variable size instructions using parallel memory banks that do not include any no-operation type codes, and corresponding method  
A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I...
6944728 Interleaving memory access  
Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second...
6944727 Interleaving apparatus and interleaving method, encoding apparatus and encoding method, and decoding apparatus and decoding method  
An interleaver which is applied to an encoding apparatus and/or a decoding apparatus in a data transmission/reception system comprises two banks of single-port RAM, and a control unit for...
6934820 Traffic controller using priority and burst control for reducing access latency  
A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an...
6934803 Methods and structure for multi-drive mirroring in a resource constrained raid controller  
Methods and associated structure for mapping of data stripes and stripes in a RAID level 1E storage subsystem such that associated stripes of multiple physical stripes are physically contiguous....
6918018 64-bit single cycle fetch scheme for megastar architecture  
The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates...
6918019 Network and networking system for small discontiguous accesses to high-density memory devices  
A networking system consists of multiple computing devices connected to multiple networking processing engines each containing a memory system including a random access device (RAM). The RAM...
6912614 Disk array apparatus and data restoring method used therein  
A controller refers to an address translation table and searches for the logical address of a valid logical block used by a host computer. Then, the controller reads from a disk array only a...
6910110 Interleaving apparatus and method for a communication system  
An interleaving apparatus and method for a communication system which can be applied to determine a new interleaver size N′=2m×(j+1) and addresses of 0 to N′−1, if a given interleaver size N is...
6910095 Memory request handling method for small discontiguous accesses to high-density memory devices  
A memory read and write request handling method is performed by a memory controller which buffers incoming memory read and write requests and distributes the requests across multiple memory banks...
6901491 Method and apparatus for integration of communication links with a remote direct memory access protocol  
In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes multiple processing cores. Multiple...
6895469 Disk array apparatus and parity processing method therein  
A controller uses an address translation table to search for a logical address of a valid logical block used by a host computer. The controller then loads from a disk array only a physical stripe...
6895488 DSP memory bank rotation  
An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules...
6886068 Disk array apparatus and data update method for storing tag blocks  
In writing all logical blocks in a data stripe in a disk array, a controller generates a logical address tag block corresponding to these logical blocks. The controller stores the logical address...
6877076 Memory controller with programmable configuration  
A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by...
6874070 System and method for memory interleaving using cell map with entry grouping for higher-way interleaving  
A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a...
6874013 Data processing arrangement and memory system  
A data processing arrangement (1) comprises a first processor (PROC1) for providing successive sets of input data, a second processor (PROC2) for receiving successive sets of output data and a...
6868486 Providing multiple memory controllers on a memory bus  
A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority...
6853643 Interleaved read/write operation in a data switch  
An interleaved read/write operation in a data switch determines a read memory of at least two memories that has been accessed during a most recent read operation. A memory controller determines a...
6848036 Method and apparatus for faster block size calculations for interleaving  
An interleaver for any modem or transmitter which transmits digital data. The interleaver eliminates the iterative divide step of a first prior art method to calculate the final depth of each...
6839820 Method and system for controlling data access between at least two memory arrangements  
A method and system for controlling an access to a first memory arrangement and a second memory arrangement. The method and system are adapted for controlling access to the first memory...
6826664 Interleaving synchronous data and asynchronous data in a single data storage file  
A method and apparatus for storing interleaved synchronous and asynchronous data in a single data storage file is disclosed. Synchronous data and asynchronous data are stored in an interleaved...
6816927 Method and system for automatic updating an access path to the system disk of a hardware perimeter of computer  
A method for automatic updating of an access path to the system disk of a hardware perimeter of computer resources during launching of an operating activity on this perimeter includes during the...
6807603 System and method for input/output module virtualization and memory interleaving using cell map  
A method of accessing a plurality of memories and a plurality of input/output modules includes providing at least one map table, including a plurality of entries. Each entry includes an entry type...
6807609 Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system  
A computer system is adapted to transfer write data from a central processing unit to one of a plurality of memory modules in a memory array by transferring a block of write data to a memory...
6804771 Processor with register file accessible by row column to achieve data array transposition  
A processor including a transposable register file. The register file allows normal row-wise access to data and also allows a transposed column-wise access to data stored in a column among...
6791557 Two-dimensional buffer pages using bit-field addressing  
Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations. In one implementation, a buffer page system includes: a data source, providing data elements in a...
6785785 Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency  
A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and...
6772271 Reduction of bank switching instructions in main memory of data processing apparatus having main memory and plural memory  
A data processing apparatus has a main memory and a plurality of memory banks. A bank switching instruction designating a particular bank address of the first memory bank is stored in an arbitrary...
6768490 Checkerboard buffer using more than two memory devices  
Methods and apparatus for storing and retrieving data in parallel but in different orders, using three or more memory devices. In one implementation, data for pixels is stored according to a...
6760743 Instruction memory system for multi-processor environment and disjoint tasks  
An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space...
6757799 Memory device with pipelined address path  
In a packetized memory device, row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address...
6756987 Method and apparatus for interleaving read and write accesses to a frame buffer  
Some embodiments of a data channel that interleaves read and write access to a frame buffer include a bit-plane storage device, a single frame buffer, a data controller and a digital pixel...