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7318115 IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic  
Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed...
7296124 Memory interface supporting multi-stream operation  
A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data...
7296112 High bandwidth memory management using multi-bank DRAM devices  
The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet...
7290079 Device and method for small discontiguous accesses to high-density memory devices  
A memory architecture design and strategy is provided using memory devices that would normally be considered disadvantageous, but by accommodating the data input, output, and other peripheral...
7290098 Method and apparatus for interleaving data streams  
In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a...
7290109 Memory system and memory card  
A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each...
7290099 Using parallelism for clear status track processing during error handling behavior in a storage system  
Tracks of meta data are cleared in a storage server by allocating task control blocks for executing associated tasks in parallel. Throttling and recycling of task control blocks is provided to...
7281081 System and method for preventing sector slipping in a storage area network  
A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover,...
7266651 Method for in-place memory interleaving and de-interleaving  
A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR...
7266668 Method and system for accessing a plurality of storage devices  
A method of accessing a plurality of storage devices is disclosed. A system and a computer program product for emulating tape libraries are also disclosed. First and second virtual storage devices...
7257688 Information processing system with redundant storage having interleaved master storage and substorage regions  
Duplicate data are stored in separate storage units SU(0) 16 and the SU(1) 26, respectively. The storage area in each of the SU(0) 16 and the SU(1) 26 is divided into master storage regions and...
7251715 Double data rate scheme for data output  
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or...
7249232 Buffering and interleaving data transfer between a chipset and memory modules  
Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory...
7233612 Wireless communication deinterleaver using multi-phase logic and cascaded deinterleaving  
A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with...
7228393 Memory interleaving  
A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read...
7225306 Efficient address generation for Forney's modular periodic interleavers  
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum....
7219200 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions  
A method of accessing matrix data of a semiconductor memory having memory banks. The memory banks each having memory cells arranged in X and Y directions, a Y decoder for selecting Y-direction...
7216199 Disk control system and method  
In a disk control system having a RAID controller for continuously writing data on a data stripe composed of a plurality disk apparatus, in response to a write request, data blocks are...
7206857 Method and apparatus for a network processor having an architecture that supports burst writes and/or reads  
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth...
7203803 Overflow protected first-in first-out architecture  
An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device...
7203805 Method and system for providing an interleaved backup  
The data from a plurality of primary data sources, such as disk drives or disk arrays, are interleaved and captured in a secondary data source, such as a tape drive, during a backup operation. The...
7185147 Striping across multiple cache lines to prevent false sharing  
A method and system for striping across multiple cache lines to prevent false sharing. A first descriptor to correspond to a first data block is created. The first descriptor is placed in a...
7171529 Single-chip microcomputer with read clock generating circuits disposed in close proximity to memory macros  
Flash ROMs operate at a speed slower than that of a CPU. In order to raise the operating speed of a single-chip microcomputer, therefore, interleaving is adopted and a plurality of flash ROMs are...
7167942 Dynamic random access memory controller  
An apparatus, and method and computer program thereof, comprises a plurality of ports each adapted to receive packets of data; a memory controller core adapted to generate one or more memory...
7167114 Memory efficient interleaving  
A method and system using a single interleaver at a either a receiving device or a transmitting device where a first symbol set is read from the single interleaver and concurrently with a second...
7143433 Video distribution system using dynamic segmenting of video data files  
A method and apparatus to dynamically segment video data files or portions of video data files within a video distribution system to facilitate the transfer of the video data files from a file...
7143234 Bios storage array  
Methods, apparatus and machine readable medium are described in which BIOS initialization code divides one or more storage devices into two or more portions. Further, a BIOS device handler may use...
7143207 Data accumulation between data path having redrive circuit and memory device  
Memory apparatus and methods accumulate data between a data path and a memory device. A memory agent may have a data accumulator between a redrive circuit and a memory device or interface. The...
7143185 Method and apparatus for accessing external memories  
A network switch that controls the communication of data frames between stations includes receive devices that correspond to ports on the network switch. The receive devices receive and store data...
7139862 Interleaving method and apparatus with parallel access in linear and interleaved order  
An interleaving method and apparatus provides parallel access in a linear and interleaved order to a predetermined number of stored data samples. A memory array with a plurality of memory devices...
7130211 Interleave control device using nonvolatile ferroelectric memory  
An interleave control device using a nonvolatile ferroelectric memory is disclosed. More specifically, a memory interleave structure using a nonvolatile ferroelectric register configured to...
7130229 Interleaved mirrored memory systems  
In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write...
7127547 Processor with multiple linked list storage feature  
A processor includes controller circuitry operative to control the storage of a plurality of separate linked list data structures for protocol data units received by the processor. The linked list...
7117317 Apparatus and method for efficient storage of data streams that each comprise separately transmitted data blocks  
A storage apparatus and method may store received data streams that each have data blocks distributed over a plurality of transmission frames. Adjacent memory addresses are allocated to store the...
7117321 System and method for interleaving SDRAM device access requests  
A method and system is provided for interleaving multiple cycles streams from clients seeking SDRAM access. More particularly, a master scoreboard register is established for enabling the...
7114040 Default locality selection for memory objects based on determining the type of a particular memory object  
One embodiment disclosed relates to a method of selecting a default locality for a memory object requested by a process running on a CPU in a multiprocessor system. A determination is made as to...
7099231 Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system  
A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier...
7099994 RAID memory system  
Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to...
7096328 Pseudorandom data storage  
Systems and techniques to pseudorandomly place and redistribute data blocks in a storage system. In general, in one implementation, the techniques include: distributing data blocks over multiple...
7093059 Read-write switching method for a memory controller  
A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists...
7093085 Device and method for minimizing puncturing-caused output delay  
Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to...
7089379 Large high bandwidth memory system  
A memory system is divided into memory subsystems. Each subsystem includes a slave controller. Each slave controller is coupled to a serial link. A master controller is coupled to the slave...
7076618 Memory controllers with interleaved mirrored memory modes  
In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second...
7073012 System and method for interleaving data in a communications device  
A system and method is provided for interleaving data in a communications device. The system includes a memory for storing symbols of a data block, a read module and a write module, each of which...
7069398 Apparatus and method for de-interleaving the interleaved data in a coded orthogonal frequency division multiplexing receiver  
An apparatus and method having a de-interleaving memory and a controller is used for de-interleaving interleaved data in a coded orthogonal frequency division multiplexing receiver. The controller...
7068281 Pixel pages optimized for GLV  
Methods and apparatus for implementing a pixel page system providing pixel pages optimized for use with a GLV (grating light valve). In one implementation, a system includes: a data source,...
7062630 Storing device for writing data onto a plurality of installed storing mediums, storing control method for the storing device, and program thereof  
A storing device can reduce the frequency of the saving operation at a step of rewriting data on the storing mediums. Where q is a size of all the data to write in storing mediums, m is the number...
7051171 Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM  
A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write...
7047357 Virtualized striping controller  
A striping disk controller and disk drive system for a computer system wherein the computer system includes a CPU connected to a system bus and executes an operating system including a BIOS, the...
7046249 Swapped pixel pages  
Methods and apparatus for implementing a pixel page system providing swapped pixel pages for use with a GLV (grating light valve). In one implementation, a swapped pixel page system includes: a...