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7996597 Mapping address bits to improve spread of banks  
A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors,...
7996601 Apparatus and method of partially accessing dynamic random access memory  
Provided are an apparatus and method for partially accessing a DRAM. The apparatus for partially accessing a DRAM includes a memory controller. The memory controller includes a first...
7979622 Memory access method  
A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is...
7979647 Method of storing data on a secondary storage device  
A backup method relies on a single secondary storage device, such as a tape storage device, which emulates multiple secondary storage devices. The emulated secondary storage devices are coupled to...
7979648 Dynamic interleaving  
Methods and apparatus provide for a Dynamic Interleaver to modify the interleaving distribution spanning physical memory modules. Specifically, dynamic interleaving provides the ability to...
7970919 Apparatus and system for object-based storage solid-state drive and method for configuring same  
An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a...
7966462 Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips  
A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a...
7966469 Memory system and method for operating a memory system  
A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The...
7945746 Memory sharing of time and frequency de-interleaver for ISDB-T receivers  
Time and frequency de-interleaving of interleaved data in an Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver includes exactly one random access memory (RAM) buffer in the...
7924763 Method and appratus for rate matching within a communication system  
A method and apparatus for rate matching is described. During operation of a transmitter, multiple data streams are received and individually interleaved with a permutation of a same length KΠ. A...
7908445 Redundant controller dynamic logical media unit reassignment  
A redundant controller storage virtualization subsystem performing host-side IO rerouting and dynamic logical media unit reassignment. In one embodiment, the assignment of logical media unit owner...
7904639 Modular command structure for memory and memory system  
A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from...
7904761 Method and apparatus for a discrete power series generator  
A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity...
7904676 Method and system for achieving varying manners of memory access  
A method and system for operating a computer system are disclosed. In at least some embodiments, the present invention relates to a method of operating a computer system that includes operating a...
7895391 Method for recording information on a record medium, record medium containing information, and method and device for reading information from a record medium  
A method for writing an audio/video information stream to an optical disc, and for reading the information from disc. The information stream includes alternative video parts which are recorded in...
7886205 Verification of a data processing system using overlapping address ranges  
Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a...
7873893 Method and apparatus for encoding and decoding data  
A method and apparatus for turbo encoding with a contention-free interleaver is provided herein. During operation an input block of size K′ is received. The original input block and the...
7873777 Flash memory system, host system for programming the flash memory system, and programming method thereor  
Provided are a multi-channel flash memory system capable of increasing the overall bandwidth by using a plurality of flash memory chips, and a programming method performed in the flash memory...
7873800 Address generator for an interleaver memory and a deinterleaver memory  
Method and device for generating an address value for addressing an interleaver memory. Consecutive address fragments to which a most significant bit(s) is to be appended are generated. Only a...
7872657 Memory addressing scheme using partition strides  
Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics...
7865657 Multi-chip flash memory device and copy-back method thereof  
A method and device for copying-back data in a multi-chip flash memory device having first and second memory chips. The method may include reading first source data from a first source region of...
7849255 Pseudo-bidimensional randomly accessible memory using monodimensional sequentially-accessiblle memory structure  
A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for...
7836263 Nonvolatile memory controlling method and nonvolatile memory controlling apparatus  
A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method...
7827348 High performance flash memory devices (FMD)  
High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least...
7818508 System and method for achieving enhanced memory access capabilities  
A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device...
7818519 Timeslot arbitration scheme  
A method for arbitrating between a plurality of access requests issued in relation to a resource by a plurality of requestors, wherein each request can be one of at least two types, a first of the...
7818501 Rebalancing of striped disk data  
Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second...
7809902 Method and system for copying DMA with separate strides by a modulo-n counter  
Provided is a system and method for de-interleaving a data stream stored in a buffer having a plurality of memory locations. Each location has a memory width of (W) bytes and the data stream is...
7802064 Flash memory system control scheme  
A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the...
7793059 Interleaving policies for flash memory  
Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be...
7793169 Intelligent table-driven interleaving  
The present invention comprises an interleaver that uses a reduced interleaving table to generate interleaved output data blocks from input data blocks. By iteratively applying the reduced...
7793048 System bus structure for large L2 cache array topology with different latency domains  
A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock...
7779198 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories  
An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B−1) each addressing more than one and less than...
7779216 Method and system of randomizing memory locations  
A memory system that disperses memory addresses of strings of data throughout a memory is provided. The memory system includes a memory, a central processing unit (CPU) and an address randomizer....
7779217 Systems for optimizing page selection in flash-memory devices  
A storage device is provided. The storage device includes a memory that includes interleaved fast and slow pages and a controller. In response to a command from a host of the storage device the...
7779215 Method and related apparatus for accessing memory  
A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of...
7778812 Selecting data to verify in hardware device model simulation test generation  
Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a...
7769973 In-place data deinterleaving  
A method for deinterleaving a sequence of interleaved data stored in a set of memory locations from a first order to a second order in-place of a memory with linear time. Two data items are...
7757054 Memory control system and memory data fetching method  
The invention discloses a memory control system and a method to read data from memory. The memory control system comprises a microprocessor, a serial storage device, a first buffer, a second...
7752379 Managing write-to-read turnarounds in an early read after write memory system  
Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read...
7746944 Electronic transmitter/receiver  
An electronic transmitter device has a puncturing device with two data outputs and/or an interleaver with two data inputs. An electronic receiver device has a de-interleaver with two data outputs...
7725641 Memory array structure and single instruction multiple data processor including the same and methods thereof  
A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data...
7721066 Efficient encoding for detecting load dependency on store with misalignment  
In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a...
7707370 Information processing apparatus, information processing method, and program  
An information processing device is provided with a plurality of memory channels, and performs interleave control on a unit memory connected to a memory channel. Furthermore, the information...
7702860 Memory access apparatus  
A memory access apparatus for accessing a first memory and a second memory, includes: an address outputting unit configured to output a read address to at least one of the first and the second...
7694193 Systems and methods for implementing a stride value for accessing memory  
Systems and methods for implementing a stride value for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a...
7689779 Memory access control in a multiprocessor system  
Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and...
7681023 Method for ensuring optimal memory configuration in a computer  
A method according to the invention ensures optimal memory configuration in a computer: A determination is made whether performance can be improved by rearranging the DIMMs that are installed in...
7676640 Flash memory controller controlling various flash memory cells  
An electronic data flash card is accessible by a host system, and includes a flash memory controller and at least one flash memory device coupled to the flash controller. The boot code and control...
7669014 Transpose memory and method thereof  
A transpose memory circuit is provided which comprises a number of dual port memory blocks each having a plurality of storage cells each configured for storing one or more data word. The dual port...