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8305384 System and method for storing and accessing pixel data in a graphics display device  
A graphics display device comprises a first and second memory, and a data transfer controller coupled with the first and second memory. In some embodiments, a method of storing pixel data...
8301850 Memory system which writes data to multi-level flash memory by zigzag interleave operation  
According to one embodiment, a memory system includes a first memory chip includes a first temporary memory and a first block, a second memory chip includes a second temporary memory and a second...
8285917 Apparatus for enhancing flash memory access  
An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data...
8281086 De-interleaving and interleaving for data processing  
Among others, techniques and apparatus are described for de-interleaving. A data processing apparatus includes a buffer to store interleaved data; an interleaving index producing unit to produce...
8276048 Resource sharing in a telecommunications environment  
A system allocates shared memory by transmitting/receiving a message specifying a maximum number of bytes of memory that are available to be allocated to an interleaver. The system determines an...
8271720 Adaptive physical allocation in solid-state drives  
A solid-state drive, a solid-state drive access unit allocation/data storage approach, and a solid-state drive access unit access/data retrieval approach are described that improve the efficiency...
8266368 Memory controller, memory system, and control method for memory system  
A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip 0 and chip 1, each of the chips...
8254243 Method and application for generating interleaver or de-interleaver  
A method and application for generating an interleaver or a de-interleaver are described. The method for generating interleaver includes: setting interleaving information of a base interleaver...
8255593 Direct memory access with striding across memory  
A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a...
8250320 Command cancellation channel for read—modify—write operation in a memory  
Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory...
8239875 Command queuing for next operations of memory devices  
Systems and/or methods that facilitate transferring data between a processor component and memory components are presented. A transfer controller component facilitates controlling data transfers...
8225027 Mapping address bits to improve spread of banks  
A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors,...
8214617 Apparatus and method of avoiding bank conflict in single-port multi-bank memory system  
Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second...
8209458 System and method for DRAM bank assignment  
A network storage system includes an address adjusting module that includes a segmented packet receiver module that receives M sections of a segmented packet, where M is an integer greater than...
8205031 Memory management system and method thereof  
The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory...
8195858 Managing conflicts on shared L2 bus  
One embodiment of the present invention sets forth a mechanism to schedule read data transmissions and write data transmissions to/from a cache to frame buffer logic on the L2 bus. When processing...
8190804 Various methods and apparatus for a memory scheduler with an arbiter  
Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in...
8190809 Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines  
A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable...
8176269 Managing metadata for data blocks used in a deduplication system  
Provided are a method, system, and article of manufacture for managing metadata for data blocks used in a deduplication system. File metadata is maintained for files having data blocks in a...
8171239 Storage management method and system using the same  
A storage management system and a storage management method are provided. The storage management system includes a host, a memory buffer, a plurality of storage blocks, and an input/output bus to...
8156294 Apparatus and method for controlling storage buffers  
Disclosed herein is a memory control apparatus including: a plurality of buffers configured to store data; a plurality of input ports configured to input the data to be written into the buffers; a...
8145877 Address generation for quadratic permutation polynomial interleaving  
For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a...
8145858 Interleave control device, interleave control method, and memory system  
According to one embodiment, an interleave control device of a memory system includes a memory divided into sections, and a data bus used, in common, for data transfers for the sections, the...
8140758 Data reorganization in non-uniform cache access caches  
Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more...
8140779 Method of storing data on a secondary storage device  
A backup method relies on a single secondary storage device, such as a tape storage device, which emulates multiple secondary storage devices. The emulated secondary storage devices are coupled to...
8135912 System and method of increasing cache size  
A system and method for increasing cache size is provided. Generally, the system contains a storage device having storage blocks therein and a memory. A processor is also provided, which is...
8132076 Method and apparatus for interleaving portions of a data block in a communication system  
Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i)...
8122208 System and method for memory architecture configuration  
Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling...
8112595 Command cancellation channel for read—modify—write operation in a memory  
Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory...
8112580 Disk drive having multiple disk surfaces accessible by a read/write head and nonvolatile memory for continuous data transfer  
A magnetic recording hard disk drive (HDD) has at least one read/write head that accesses more than one disk surface. The HDD is able to transfer data to and from the host computer seamlessly...
8108633 Shared stream memory on multiple processors  
A method and an apparatus that allocate a stream memory and/or a local memory for a variable in an executable loaded from a host processor to the compute processor according to whether a compute...
8108625 Shared memory with parallel access and access conflict resolution mechanism  
Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple...
8095743 Memory access control in a multiprocessor system  
Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and...
8090915 Packet transmission control apparatus and method  
A packet transmission control apparatus includes a plurality of controllers, an arbitrator, a BUSY control circuit, and a memory. The controller controls a transmission of a packet to an interface...
8082413 Detection circuit for mixed asynchronous and synchronous memory operation  
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address...
8078797 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices  
A memory storage system of an embodiment includes a nonvolatile memory unit and memory control circuitry coupled to the memory unit. Storage locations of the memory unit are organized into one or...
8072463 Graphics system with virtual memory pages and non-power of two number of memory elements  
A graphics system utilizes virtual memory pages and has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory...
8069318 High performance data rate system for flash devices  
A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal...
8060708 Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory  
A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from...
8060692 Memory controller using time-staggered lockstep sub-channels with buffered memory  
Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two...
8051250 Systems and methods for pushing data  
A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the...
8051239 Multiple access for parallel turbo decoder  
A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to...
8046542 Fault-tolerant non-volatile integrated circuit memory  
Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively...
8032800 Subframe interleaving  
Included are embodiments for subframe interleaving. At least one embodiment of a method includes receiving at least one subframe, the at least one subframe being derived from a plurality of frames...
8027394 Reducing data stream jitter during deinterleaving  
In one embodiment, the present invention includes a deinterleaver having an input interface to receive orthogonal frequency division multiplexing (OFDM) symbols from a demodulator, a memory...
8010755 States encoding in multi-bit flash cells for optimizing error rate  
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of...
8010764 Method and system for decreasing power consumption in memory arrays having usage-driven power management  
A method and system for decreasing power consumption in memory arrays having usage-driven power management provides decreased power consumption in the memory array of a processing system. Per-page...
8006048 Signal processing circuit  
A signal processing circuit includes a signal processing section which generates first address data and second address data in accordance with data processing, reads data stored in an external...
7996646 Efficient encoding for detecting load dependency on store with misalignment  
In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a...
7996615 Cache region concept  
A method to associate a storage policy with a cache region is disclosed. In this method, a cache region associated with an application is created. The application runs on virtual machines, and...