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8607126 Resource sharing in a telecommunications environment  
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple...
8606988 Flash memory control circuit for interleavingly transmitting data into flash memories, flash memory storage system thereof, and data transfer method thereof  
A flash memory control circuit including a microprocessor unit, a first interface unit, a second interface unit, a buffer memory, a memory management unit, and a data read/write unit is provided....
8595459 Micro-threaded memory  
A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access...
8589642 Computer system duplicating writes by synchronous remote copy with multiple host computers using heterogeneous operating systems  
A computer system having a plurality of host computers and a storage system is provided which allows any one host computer to perform a global copy operation on any arbitrary or all storage areas...
8589615 System and method for DRAM bank assignment  
A network device includes memory having memory banks, and a packet processor module configured to receive bursts of packets and segment a received packet into a plurality of sections corresponding...
8578098 System and method for increasing cache size  
A system and method for increasing cache size is provided. Generally, the system contains a memory and a processor. The processor is configured by the memory to perform the steps of: categorizing...
8560761 Memory resource management for a flash aware kernel  
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory...
8527676 Reducing latency in serializer-deserializer links  
A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on...
8520496 Method and apparatus for rate matching within a communication system  
A method and apparatus for rate matching is described. During operation of a transmitter, multiple data streams are received and individually interleaved with a permutation of a same length KΠ. A...
8516149 System for operating NFSv2 and NFSv3 clients with federated namespace  
An information retrieval system having: a client adapted for accessing a plurality of file sets stored on one of a plurality of file servers; a plurality of file servers configured to operate with...
8495473 Resource sharing in a telecommunications environment  
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple...
8484397 Various methods and apparatus for a memory scheduler with an arbiter  
Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in...
8484532 Random-access multi-directional CDMA2000 turbo code interleaver  
An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address...
8478928 Data storage device and information processing system incorporating data storage device  
A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory...
8468295 System and method for reducing power consumption of memory  
Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include...
8468410 Address generation apparatus and method for quadratic permutation polynomial interleaver  
An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality...
8464009 Method for memory interleave support with a ceiling mask  
A distributed shared memory multiprocessor system that supports both fine- and coarse- grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the...
8464008 Command cancellation channel for read-modify-write operation in a memory  
Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory...
8452899 Data allocation in a distributed storage system  
A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with...
8443147 Memory interleave for heterogeneous computing  
A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by...
8438434 N-way parallel turbo decoder architecture  
Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying...
8433976 Row column interleavers and deinterleavers with efficient memory usage  
Interleaver designs and interleaving methods that perform block-wise interleaving by reading blocks into and out of memories, where a block can be written to the memory before another block has...
8433844 Method for managing a memory device having multiple channels and multiple ways, and associated memory device and controller thereof  
A method for managing a memory device having multiple channels and multiple ways includes: with regard to a logical page, finding a Flash memory chip for being written from a plurality of Flash...
8429352 Method and system for memory block flushing  
A method and system for flushing physical memory blocks in a memory device is disclosed. The method includes detecting a quantity of available memory, background flushing partially obsolete memory...
8423864 Receiving apparatus, receiving method, program, and receiving system  
A receiving apparatus includes: a deinterleaving device configured to perform a deinterleaving process on an LDPC-coded data signal having undergone an interleaving process, the LDPC representing...
8423708 Method of active flash management, and associated memory device and controller thereof  
A method of active Flash management is provided. The method is applied to a controller of a memory device, where the controller is utilized for accessing a Flash memory in the memory device, and...
8413240 Information processing device, information processing method, and computer readable recording medium  
An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data...
8412893 Data storage device and method for handling data read out from memory using a ping-pong buffer  
The invention provides a method for handling data read out from a memory. In one embodiment, a controller corresponding to the memory comprises a ping-pong buffer. First, a first sector read time...
8407407 Solid state drive access control system with equalized access timing  
A drive control module of a solid-state drive (SSD) includes a first module that receives host commands from one of a host command buffer and a drive interface of the SSD, converts the host...
8407432 Cache coherency sequencing implementation and adaptive LLC access priority control for CMP  
A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access...
8407433 Interconnect implementing internal controls  
In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the...
8402152 Apparatus and system for object-based storage solid-state drive  
An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a...
8402233 Method and apparatus for high throughput mass storage device interface in a microprocessor for handheld systems  
Certain embodiments of a method and apparatus for high throughput mass storage device interface in a microprocessor for handheld systems may comprise interleaving accesses to a plurality of mass...
8402199 Memory management system and method thereof  
The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory...
8397123 Recursive realization of polynomial permutation interleaving  
Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of...
8392673 Data writing/reading method, a de-interleaving method, a data processing method, a memory and a memory drive apparatus  
A data writing/reading method, a de-interleaving method, a data processing method, a memory, and a memory drive are provided whose costs are reduced. When a plural data interleaved in transmitter...
8386727 Supporting interleaved read/write operations from/to multiple target devices  
Bus transactions in a computer network are improved by utilizing a multicast transaction from a single initiator to multiple targets. The multiple targets simultaneously execute the transaction...
8386706 Method and system for secure data storage  
A method and system for secure data storage and retrieval is provided. A sequence of data units is divided into multiple subsets of data units corresponding to multiple data channels. The multiple...
8375187 I/O scheduling for flash drives  
In a data storage system, a controller schedules I/Os to storage devices so that each one substantially performs only reads or only writes, thereby increasing performance. At least one storage...
8375238 Memory system  
A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data...
8364916 Method and apparatus for implementing interleaving and de-interleaving at second time  
A method for second interleaving is disclosed. The method comprises: generating an interleaving address preset in an interleaving matrix for each input data, and writing the data into the...
8356147 Tiered storage pool management and control for loosely coupled multiple storage environment  
A system comprises a first storage system including a first storage controller, which receives input/output commands from host computers and provides first storage volumes to the host computers;...
8352808 Data storage system and device with randomizer/de-randomizer  
A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined...
8347020 Memory access controller, systems, and methods for optimizing memory access times  
A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access...
8335956 Packet retransmission and memory sharing  
Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of...
8332607 Non-volatile memory storage device and operation method thereof  
A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits...
8332701 Address generation apparatus and method for quadratic permutation polynomial interleaver de-interleaver  
An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit...
8332569 Nonvolatile memory system using data interleaving scheme  
A memory system comprises a plurality of nonvolatile memory devices configured for interleaved access. Programming times are measured and recorded for various memory cell regions of the...
8327092 Memory device configurable as interleaved or non-interleaved memory  
A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of...
8316190 Computer architecture and method of operation for multi-computer distributed processing having redundant array of independent systems with replicated memory and code striping  
Computers and other computing machines and information appliances having a modified computer architecture and program structure which enables the operation of an application program concurrently...