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5341486 Automatically variable memory interleaving system  
An automatically variable memory interleaving system which provides different interleaving factors for particular groups of memory modules dependent upon the number of operable modules present in...
5333291 Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination  
A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex...
5325500 Parallel processing units on a substrate, each including a column of memory  
Parallel processing circuitry on a substrate includes an array of memory elements in rows and columns. Row select circuitry can select the memory elements in any of the rows. Each column has...
5323489 Method and apparatus employing lookahead to reduce memory bank contention for decoupled operand references  
A data storage system for interleaved memory banks employs a lookahead search of data request addresses to reduce the impact of bank collisions. The system permits out of order load and store...
5313603 Arrangement of controlling memory access requests to grouped memory banks  
A plurality of banks is divided into a plurality of bank groups and a pair of read and write data control registers is assigned to each of the bank groups. A memory main controller is operatively...
5301292 Page mode comparator decode logic for variable size DRAM types and different interleave options  
Apparatus for decoding and comparing memory addresses which determines DRAM size and interleave options utilized is disclosed. A row address and bank select bits are decoded and latched and are...
5293607 Flexible N-way memory interleaving  
The invention comprises methods and apparatuses for interleaving a number of memory cards of different sizes. A restricted range modulo-N adder for identifying and selecting the correct interleave...
5289584 Memory system with FIFO data input  
At least two double buffers or FIFOs, each FIFO including a first group of latches in series with a second group of latches, coupled between a host data bus and a corresponding bank or way of...
5287477 Memory-resource-driven arbitration  
A method and apparatus to improve memory performance in a computer bus system. Memory is divided into interleaved blocks and memory addresses are mapped into block identification numbers. Master...
5283877 Single in-line DRAM memory module including a memory controller and cross bar switches  
A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line...
5280594 Architecture for high speed contiguous sequential access memories  
In accordance with the present invention, by interleaving two banks of memory output registers, a memory system is provided which allows an indefinite number of sequential accesses to contiguous...
5274788 High speed memory access for a data processor  
A data processor which includes a central processing unit (CPU) coupled to an address bus for supplying an address to an external memory and a data bus for supplying data to the external memory...
5261068 Dual path memory retrieval system for an interleaved dynamic RAM memory unit  
A digital computer having a dual path memory retrieval system for a dynamic RAM memory unit comprised of any number of interleaved memory banks. The system includes means for asserting and...
5247644 Processing system with improved sequential memory accessing  
A processing system provides efficient accessing by a processor of a memory during a sequential memory access. The processing system includes a memory having a plurality of storage locations, each...
5243701 Method of and system for processing data having bit length variable with modes of operation  
Data processing system including memory device having even-numbered addresses and odd-numbered addresses in which both an even-numbered address and an odd-numbered address are accessed in the long...
5241665 Memory bank comparator system  
A memory bank comparator system in a memory system including a plurality of memory banks determines, on a cycle-by-cycle basis, whether a memory address is valid, which one of the memory banks is...
5226134 Data processing system including a memory controller for direct or interleave memory accessing  
A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank...
5206942 Partially storing control circuit used in a memory unit  
Partial-store access in which a portion of data is changed, is performed using a plurality of memory banks in a memory unit. The partial store-access is performed through an interleave method in...
5161221 Multi-memory bank system for receiving continuous serial data stream and monitoring same to control bank switching without interrupting continuous data flow rate  
A method and apparatus for the handling of high speed data in which the data is routed to a plurality of memory arrays. In order to provide for the handling of a continuous stream of data at a...
5111385 Parallel-mode data transfer apparatus using sector memories  
A data transfer apparatus comprises first and second memories each having a plurality of sectors each having the storage capacity of each sector in a storage disk. First and second memory access...
5063533 Reconfigurable deinterleaver/interleaver for block oriented data  
A reconfigurable deinterleaver for deinterleaving up to N interleaved codewords, each up to M bits in length comprises a memory array, a memory for storing predetermined deinterleaver parameters,...
5051889 Page interleaved memory access  
The present invention provides a memory organization scheme for a high-performance memory controller. The memory organization of the present invention combines page mode techniques and...
5016167 Resource contention deadlock detection and prevention  
In a multiprocessor system with an interleaved memory, predicted busy terms for interleaves of the main store being accessed are sent to each processor in the system, so that they will not waste...
4964037 Memory addressing arrangement  
A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to...
4918600 Dynamic address mapping for conflict-free vector access  
Conflict-free vector access of any constant stride is made by preselecting a storage scheme for each vector based on the accessing patterns to be used with that vector. A respective storage scheme...
4914575 System for transferring data between an interleaved main memory and an I/O device at high speed  
An input/output channel apparatus includes a system bus controller for generating a memory read request and outputting a memory address. Generation of the memory read request is inhibited in...
4875161 Scientific processor vector file organization  
A vector file organization for a multiple pipelined vector processor with data transfer capability to support multiple program execution pipelines. Multiple pipelines can simultaneously access...
4866603 Memory control system using a single access request for doubleword data transfers from both odd and even memory banks  
A memory access control system has a main memory having a plurality of memory banks divided into two groups, thus enabling parallel processing for data, a command/address bus line, a write data...
4839796 Static frame digital memory  
A digital memory system wherein a plurality of frames in the memory, each frame holding a page of data, may be rapidly accessed utilizing static column dynamic random access memories (SCRAMs). The...
4811280 Dual mode disk controller  
A dual mode disk controller is disclosed for use between a host processor and its storage medium for controlling data transfer to and from the storage medium. The data is formatted on the medium...
4803655 Data processing system employing a plurality of rapidly switchable pages for providing data transfer between modules  
An execute module in a data processing system is provided with a randomly accessible scratchpad memory which is logically divided into two switchable pages. During operation one page can be...
4783736 Digital computer with multisection cache  
A digital computer including a plurality of memory elements, the memory elements being interleaved (i.e., each is assigned memory addresses on the basis of a low order portion of the memory...
4755933 Data Processor system having look-ahead control  
A data processor system is set up with, at least, a main memory and a central control unit. The main memory stores therein instructions to be executed by the central control unit. The main memory...
4740911 Dynamically controlled interleaving  
A data processing system in which interleaving among memory controllers may be controlled. The interleaving is carried out on a double-word basis, and the state of the double-word address bit is...
4737931 Memory control device  
A memory system in which a plurality of memory blocks are interleaved includes a temporary storage buffer, for example, a first-in, first-out buffer, for temporarily storing the data read out from...
4674032 High-performance pipelined stack with over-write protection  
A high performance pipelined virtual first-in first-out stack structure having a data stack portion and a split control stack portion is described. The stack structure is intended for use in a...
4663732 Apparatus for storing and retrieving data in predetermined multi-bit quantities containing fewer bits of data than word length quantities  
An apparatus for storing and retrieving data in predetermined multi-bit length quantities containing fewer bits of data than word length quantities, including a memory for storing word length...
4600986 Pipelined split stack with high performance interleaved decode  
A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high...
4558429 Pause apparatus for a memory controller with interleaved queuing apparatus  
A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller...
4479180 Digital memory system utilizing fast and slow address dependent access cycles  
An improved addressing circuit for memory system using a plurality of integrated circuit memory arrays is disclosed. Typical integrated digital memory arrays include an address input which accepts...
4451880 Memory controller with interleaved queuing apparatus  
A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a...
4435765 Bank interleaved vector processor having a fixed relationship between start timing signals  
The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational...
4393444 Memory addressing circuit for converting sequential input data to interleaved output data sequence using multiple memories  
A system for converting sequentially received data words, in the form of successively received groups of data words, into an interleaved output data word sequence, with each group of received data...
4376972 Sequential word aligned address apparatus  
A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory...
4323965 Sequential chip select decode apparatus and method  
A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory...
4314333 Data processor  
A data processor used with a host computer is constructed by a plurality of memory units, at least one arithmetic and logic unit, a register file and a microprogram memory for storing...
4293910 Reconfigurable key-in-storage means for protecting interleaved main storage  
The disclosure provides a storage protection (SP) array in each of two system controllers (SCs) in a multiprocessing system which has a shared main storage containing a plurality of basic storage...
4156926 PROM circuit board programmer  
A PROM programmer programs an array of PROMs mounted on a circuit board. The PROM chips are selectively addressed by energization of the respective chip with a high write voltage or a low read...
4027291 Access control unit  
An access control unit for controlling a memory device having a plurality of memory units for storing data in a manner whereby the memory units are accessed sequentially, comprises a data register...
4008462 Plural control memory system with multiple micro instruction readout  
A microprogramming control system employing a plurality of low read rate control memories, for storing micro instructions, individually addressed in turn at a rate greater than the read rate of...