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5768624 Method and apparatus for employing ping-pong buffering with one level deep buffers for fast DRAM access  
A memory access chip set includes a data buffer chip and a system controller chip. The data buffer chip contains storage elements that buffer data values transferred between a memory and either...
5765212 Memory control circuit that selectively performs address translation based on the value of a road start address  
A memory control circuit improves the read speed of a program memory stored in a ROM. The memory control circuit includes a memory divided into four blocks, an address translation circuit for...
5765182 Interleaving memory on separate boards  
This invention relates to an improved memory storage system which allows interleaving between two separate memory banks. In this way, data can be retrieved simultaneously from the two memory banks...
5761695 Cache memory control method and apparatus, and method and apparatus for controlling memory capable of interleave control  
In a memory control apparatus which has a main memory constructed by a plurality of memory areas and a cache memory which can be accessed at a speed higher than that of the main memory and in...
5761472 Interleaving block operations employing an instruction set capable of delaying block-store instructions related to outstanding block-load instructions in a computer system  
A computer system which includes a processor having an instruction set capable of "delaying" block-store instructions related to any outstanding block-load instruction(s). Accordingly, a method...
5761732 Interleaving for memory cards  
A method and apparatus for interfacing a memory card with a system having a smaller bus width while maintaining its interchangeability with other systems having larger bus widths. The host...
5758092 Interleaved bitrate control for heterogeneous data streams  
A heterogeneous multimedia stream has interleaved samples of two or more different substream types. For example, a heterogeneous video stream may have interleaved intra, predicted, and...
5752037 Method of prefetching data for references with multiple stride directions  
There are two separate, yet related, prefetching strategies used for data references used having multiple strides, which typically occur in data references within nested loop structures. The first...
5745915 System for parallel reading and processing of a file  
A system for parallel reading and processing of a file. The system includes multiple disks for storing the file. The disks are coupled to a data processing system via multiple input-output...
5742788 Method and apparatus for providing a configurable display memory for single buffered and double buffered application programs to be run singly or simultaneously  
An arrangement providing frame buffer memory for an output display by which single buffer and double buffered application programs may be run singly or simultaneously is described. An array of...
5740402 Conflict resolution in interleaved memory systems with multiple parallel accesses  
A conflict resolution system for interleaved memories in processors capable of issuing multiple independent memory operations per cycle. The conflict resolution system includes an address bellow...
5737572 Bank selection logic for memory controllers  
A system and method for controlling DRAM is described. According to exemplary embodiments of the present invention, a memory subsystem can be populated by end users with any of a variety of DRAM...
5737252 Circuit arrangement comprising a permutation unit and method of processing a batch of items  
A circuit arrangement calculates pseudo-random permutations of a set of numbers. Including compositions of some basic pseudo-random permutations and the inverse permutations of permutations that...
5734862 System for selectively buffering and displaying relevant frames from interleaving frames associated with respective animation sequences stored in a medium in response to user selection  
A system for eliminating access time in CD-ROM based interactive video applications. A CD-ROM disc is formatted with multiple interleaved animation sequences. During playback, a user is able to...
5701434 Interleave memory controller with a common access queue  
A computer system is composed of a processor 10, a memory control circuit 70, and interleaved bank memories 41 through 44. The memory control circuit contains random access queue entries 71...
5687341 Device for speeding up the reading of a memory by a processor  
The device embodying the invention uses at least two read-only memory blocks containing the instructions of the application code and of which the addressing inputs are respectively connected to...
5684973 Expandable memory system and method for interleaving addresses among memory banks of different speeds and sizes  
An expandable memory system and a method for operating a memory system having a variable number of memory banks are described. The memory system can utilize a variable number of separately...
5680579 Redundant array of solid state memory devices  
A device employing a redundant array of solid state memory devices is presented, whereby RAID technology architecture is uniquely combined with solid state memory devices. The devices comprises a...
5668974 Memory with variable levels of interleaving and associated configurator circuit  
A memory having variable interleaving levels and associated configurator circuit which provides for the optimum level of interleaving based on the memory configuration. A number of independently...
5659713 Memory stream buffer with variable-size prefetch depending on memory interleaving configuration  
A read buffering system and method employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so...
5652861 System for interleaving memory modules and banks  
A memory system for a digital computer has first and second memory modules having differing numbers of independently-accessible banks and unlike capacities. The digital computer also has an...
5651138 Data processor with controlled burst memory accesses and method therefor  
A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data...
5644780 Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors  
A high speed register file is provided for use with Very Long Word Instruction (VLIW) and N-way superscaler processors. The high speed register file includes a selected number of copies of a...
5638533 Method and apparatus for providing data to a parallel processing array  
A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data...
5630098 System and method for interleaving memory addresses between memory banks based on the capacity of the memory banks  
The invention is a system and method for accessing a plurality of memory banks. The system includes a number of memory banks, a register and a controller. The register stores capacity information...
5619679 Memory control device and method operated in consecutive access mode  
A memory control device and method receives a request to transfer a series of first-unit K byte (for example, 512) data in an address space, divides the first-unit K into second-unit L (for...
5598551 Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles  
By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition...
5596740 Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks  
A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A...
5592653 Interface conversion device  
An interface conversion device performs a conversion between input data streams and standard interfaces with the same information rate. The device may comprise a first line receiver (RX1) for a...
5592640 Data processing apparatus capable of reading data from different-format CD-ROMS according to different processing methods of the data  
A data processing system, which includes a CD-ROM drive, addresses data in a CD-ROM and commands the CD-ROM drive to read the data. The data processing system selects one of a plurality of control...
5590299 Multiprocessor system bus protocol for optimized accessing of interleaved storage modules  
A multiprocessor information processing system has a system bus with interleaved memory modules in communication with multiple CPUs. The multiprocessor system includes a subsystem monitoring...
5572691 Apparatus and method for providing multiple data streams from stored data using dual memory buffers  
An apparatus and method are disclosed for processing successive frames of data to provide a plurality of data streams containing the data in different orders. In an illustrated embodiment, two...
5561777 Process for sequentially reading a page from an image memory in either of two directions  
A process of loading an image in the form of a bit map into a memory which can transfer data words in burst mode in either row or column direction. First, the memory is divided into two sections...
5561784 Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses  
A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined...
5559986 Interleaved cache for multiple accesses per clock cycle in a microprocessor  
An interleaved cache is used for multiple data accesses per clock in a microprocessor. The cache includes a storage array having multiple banks of single-ported memory cells for storing data, a...
5559990 Memories with burst mode access  
To provide a boundaryless burst mode access, a memory array is divided into two or more subarrays. Each subarray has its own row and column decoders. The columns of each subarray are divided into...
5539902 Vector data processing apparatus wherein a time slot for access to a bank of vector registors is assigned based on memory access time information  
A vector data processing apparatus having a set of vector registers, one or more memory access pipelines, and one or more composite calculation pipelines, wherein the vector registers consist of a...
5537577 Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions  
An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered...
5535333 Adapter for interleaving second data with first data already transferred between first device and second device without having to arbitrate for ownership of communications channel  
A system and method for controlling a communications adapter interface such that supplemental data can be interleaved with data being transferred. The interleaving is performed in a manner such...
5530837 Methods and apparatus for interleaving memory transactions into an arbitrary number of banks  
Methods and apparatus are provided for interleaving memory transactions into an arbitrary number of memory banks that need not be equal size. A memory address range is divided into subranges of...
5530828 Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality of flash memories  
A semiconductor storage device such as a disk pack includes a plurality of flash memories, a write buffer memory in which data are temporarily held, a processor which controls data writing and...
5522060 Multiprocessor memory managing system and method for executing sequentially renewed instructions by locking and alternately reading slave memories  
A multiprocessor memory managing system and method make it possible for a series of instructions corresponding to a data set, which is sequentially renewed by a series of data, to be sequentially...
5506978 Memory apparatus including a shift circuit for shifting a word select signal by a predetermined number of words  
A memory apparatus and a data processor using the same, wherein a shift circuit 12 which shifts a word select signal generated by an address decoder 11 by a predetermined number of words and gives...
5504871 Memory controller having bus master for addressing instruction memories  
Instruction memories and a data memory are connected to a bus master which inputs or outputs an address signal and a data signal. The instruction memories are interleaved and are driven by a...
5497478 Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles  
A memory access system and method is provided to modify a memory interleaving scheme so that data can be read from a memory system in any sequence without inserting a waiting cycle. Even...
5463755 High-performance, multi-bank global memory card for multiprocessor systems  
A multi-bank global memory system (GMS) for use with a multiprocessor computer system having a global bus. The GMS includes up to four global memory cards (GMCs) connected to the global bus. The...
5461718 System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory  
A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system...
5412788 Memory bank management and arbitration in multiprocessor computer system  
A memory management and arbitration technique that reduces system bus contention by eliminating memory bank conflicts employs a restrictive, distributive memory-arbitration scheme, and an improved...
5386537 System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving  
A data processor adopts a CPU that is represented by an RISC type CPU and capable of processing one instruction in one clock cycle. The data processor has an instruction bus and a data bus...
5341489 Memory card with programmable interleaving  
A memory card that is detachably connectable to a host data processing system includes a plurality of flash EPROM memory devices for storing data input from the host system in addressable data...