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6098157 Method for storing and updating information describing data traffic on a network  
A method for storing and updating records in a first table containing information corresponding to specific nodes of a network, and in a second table containing information corresponding to a...
6075828 Receiver de-interleaving means and a method for a reduced time de-interleaving memory  
A DAB receiver in which a reduced time de-interleaving memory for storing metrics is used, but which still allows processing of DAB services which normally would exceed the storage capacity of the...
6073203 Method for the continuous readout of a data sequence from a memory  
For the continuous and interruption-free readout of a data sequence predetermined by a predetermined address sequence from a memory that is constructed of dynamic memory components (DRAM or SDRAM)...
6049855 Segmented memory system employing different interleaving scheme for each different memory segment  
A computer system has first and second random access memory (RAM) modules for storing digital information, and first and second system controllers coupled to the first and second RAM modules,...
6041387 Apparatus for read/write-access to registers having register file architecture in a central processing unit  
A data processing unit has a set of data registers and a set of address registers. Each register has a width of n bits. Furthermore, there are provided address load and store buffers associated...
6041393 Array padding for higher memory throughput in the presence of dirty misses  
An array padding technique is described that increases memory throughput in the presence of dirty misses. The technique pads arrays so that the starting addresses of arrays within a target loop...
6038559 Segment aggregation in a geographic database and methods for use thereof in a navigation application  
A geographic database for use with a navigation application program that provides navigation features to an end-user. The geographic database includes data entities that represent segments of...
6032225 Microprocessor system with burstable, non-cacheable memory access support  
A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where...
6026473 Method and apparatus for storing data in a sequentially written memory using an interleaving mechanism  
A method and apparatus for storing data values received within respective cycle periods of a clock signal are disclosed. Data values are alternately stored in first and second data hold registers...
6003110 Method and apparatus for converting memory addresses into memory selection signals  
A method and system for converting memory addresses into memory selection signals wherein memory modules are inserted into insertion regions of a memory and logical capacity and configuration...
6000019 SDRAM data allocation system and method utilizing dual bank storage and retrieval  
A system and method for allocating data among first and second banks of at least one SDRAM, the data including first, second and third words to be accessed during consecutive read operations. The...
5995080 Method and apparatus for interleaving and de-interleaving YUV pixel data  
An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas...
5996053 Method and apparatus for fetching classified and stored information  
A method for selectively fetching a piece of reference information that is stored in a storage location with a highest priority that is determined beforehand if plural pieces of reference...
5991853 Methods for accessing coincident cache with a bit-sliced architecture  
A "bit-sliced" construction of our cache module dictates dual TAG RAM structures and dual invalidation queues, yielding enhanced performance. By putting half the TAG array in each of two cache...
5991857 Interleaving and de-interleaving of data in telecommunications  
An interleaving process in which data is interleaved or interleaved data is de-interleaved. Input data units are distributed over a plurality of output groups of data units. In GSM telephony,...
5987574 Bank arbitration for SDRAM memory control  
A memory controller for a special purpose digital video processor. To achieve a speed enhancement when using multiple bank memory such as SDRAM, the memory controller arbitrates requests for...
5987569 Memory control apparatus and method for controlling usage amounts for a plurality of cache memories  
A memory control apparatus interposed between a central processing unit and a memory device to store data includes a channel control unit to control a data transfer to/from the central processing...
5983388 Forward error correction arrangement (FEC) for multipoint to single point communication systems  
A forward error correction (FEC) system and method for use in a multipoint-to-point frame based synchronized transmission communication system in which data from users are sent in selected...
5983328 Data processing device with time-multiplexed memory bus  
A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external...
5968200 Implied interleaving a family of systematic interleavers and deinterleavers  
Apparatus that realizes a substantial advantage by employing implied interleaving to create a systematic interleaver, that can result in a superior block error rate compared to the current data...
5959640 Display controllers  
An LCD panel controller includes a panel display driver driving a display panel having an inherent line input buffer, a memory/interface block, a frame memory and a host computer. The memory...
5953743 Method for accelerating memory bandwidth  
A computer system and method process memory requests for access to a computer memory. The computer system arbitrates between current memory requests based on an immediately previous memory request...
5950220 Method and apparatus for providing a logical double sided memory element by mapping single sided memory elements onto a logical double sided memory address space  
A mapping unit is described for use in a computer system having a multiple bank memory. Each bank of the multiple bank memory includes a plug-in socket defining first and second memory rows. The...
5946496 Distributed vector architecture  
A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical...
5938748 Data transfer mechanism for transfer of real-time data including real-time data computed on-the-fly  
A data transfer mechanism for a serial interface is provided whereby data transfer may be precisely controlled, eliminating the need for significant buffering. The data transfer mechanism also...
5940863 Apparatus for de-rotating and de-interleaving data including plural memory devices and plural modulo memory address generators  
An apparatus for re-rotating and deinterleaving data includes (i) a first memory for storing D elements of rotated and interleaved data in D storage locations, (ii) a first addresser for...
5935230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs  
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID...
5930483 Method and apparatus for communications control on a small computer system interface  
A method and apparatus are provided for controlling communications on a small computer system interface (SCSI). A cache memory is arranged for storing an input queue, a status queue and a cache...
5924111 Method and system for interleaving data in multiple memory bank partitions  
A method and system for performing 2n -way interleaving of data words over P memory banks is disclosed. Each of the memory banks is partitioned into 2n partitions. The data word (pixel) address...
5915126 Computer system memory controller and method of burst data ordering translation  
A computer system including a memory controller programmed with associated burst order translation logic and coupled to one or more microprocessors and including a memory circuit which supports...
5913069 Interleaving memory in distributed vector architecture multiprocessor system  
A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory....
5909693 System and method for striping data across multiple disks for continuous data streaming and increased bus utilization  
A system and method for storage and continuous delivery of a plurality of data files in a data stream are disclosed. The system and method include storing at least one data file of the plurality...
5900885 Composite video buffer including incremental video buffer  
A method for providing a video buffer includes reserving an incremental video buffer in system memory, and controlling the use of a dedicated video buffer and the incremental video buffer to...
5848437 Method of and system for interleaving real-time files with different periods  
A method and a system for the interleaving of real-time files so as to form an interleaved combination for storage or transmission. They can be used for a multimedia application in which real-time...
5848428 Sense amplifier decoding in a memory device to reduce power consumption  
A multiple-way cache memory system incorporating circuitry for selectively enabling the sense amplifiers in a given memory bank only when the memory bank contains data that is being accessed. In...
5845329 Parallel computer  
A parallel computer includes a plurality of processors arranged in a taurus mesh network, with each processor having a local memory, and a plurality of secondary storage units. The network is...
5835952 Monolithic image data memory system and access method that utilizes multiple banks to hide precharge time  
An image data memory with a 2-bank (bank A and bank B) structure is disclosed. The bank A stores only even field data, whereas the bank B stores only odd field data, and a peripheral circuit...
5832216 Network adapter having single ported memory which is accessible by network and peripheral bus on a time division multiplexed (TDM) basis  
This invention relates to an improved LAN adapter. The LAN adapter includes a time division multiplex (TDM) ported RAM. The RAM is used to provide both network data FIFOs and control data storage...
5828877 Circuit and method for optimizing creation of a compressed main memory image  
A computer system having a central processing unit ("CPU"), a main memory divisible into allocable units, a secondary storage unit and an operating system for allocating the allocable units to...
5828671 Method and apparatus for deinterleaving an interleaved data stream  
A method and apparatus deinterleave data blocks each transmitted as a sequence of data groups including N bits of data from a single bit position of N words. A first data block is received (1004)...
5819106 Method of transposing data buffer by selectively merging pairs of rows, interleaving two operands of equal length yielding output twice the length of each operand  
A method of transposing data. Either eight bit or sixteen bit data is placed in a buffer. Each buffer is defined to contain one or more sub-buffers. Rows of the sub-buffer are selectively...
5813037 Multi-port register file for a reservation station including a pair of interleaved storage cells with shared write data lines and a capacitance isolation mechanism  
A multi-port register file suitable for use in a reservation station in a superscalar microprocessor. The multi-port register is a static random access memory (SRAM) array which interleaves the...
5809555 Method of determining sizes of 1:1 and 2:1 memory interleaving in a computer system, configuring to the maximum size, and informing the user if memory is incorrectly installed  
A method for configuring memory in a computer system. The method calls for determining the maximum configurable size of installed memory modules for each of a plurality of interleave options. The...
5809539 Processor system having address allocation and address lock capability adapted for a memory comprised of synchronous DRAMs  
In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example,...
5805917 Parallel processing system with a plurality of communication register modules  
A parallel processing system includes a plurality of processors, a plurality of communication register modules each including a communication register, and an interconnecting network for...
5802589 Data buffering apparatus for buffering imaging data between a raster image processor (RIP) and an output device  
A method and apparatus for providing data buffering through a plurality of storage buffers between at least one raster image processor (RIP) and at least one output device in an imaging system....
5787454 Recorder buffer with interleaving mechanism for accessing a multi-parted circular memory array  
A buffer comprises a memory array, a write circuit and a read circuit. The memory array comprises one or more memory banks. Each of the memory banks is made up of a plurality of memory cells. Each...
5781201 Method for providing improved graphics performance through atypical pixel storage in video memory  
A method for improving the performance of a graphics system includes the steps of allocating appropriate pixels to slices of memory such that corresponding subsets of bits of neighboring pixels...
5778412 Method and apparatus for interfacing a data bus to a plurality of memory devices  
A method and apparatus for interfacing a data bus to a plurality of memory devices. A portion of data associated with a first address is loaded into a first cell in a first memory device. Another...
5768559 Multiple bank structured memory access device having flexible setting of a pipeline stage number  
A memory access device including a memory unit having a plurality of independently accessible banks and a pipeline stage number setting unit for setting the number of the pipeline stages in a...