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6339813 |
Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory
In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling...
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6339816 |
Method for improving controllability in data processing system with address translation
When there are write accesses to user pages in a data processing system that are marked as write-protected in a translation memory, the method checks, after an interrupt request, a corresponding...
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6338125 |
Dynamic slot allocation and tracking of multiple memory requests
A microprocessor having a logic control unit and a memory unit. The logic control unit performs execution of a number of instructions, among them being memory operation requests. A memory operation...
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6338123 |
Complete and concise remote (CCR) directory
A method and structure for a system for maintaining coherence of cache lines in a shared memory multiplexor system comprises a system area network and a plurality of compute nodes connected to the...
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6334173 |
Combined cache with main memory and a control method thereof
A combined cache with main memory and a control method thereof, which can be configured with various structures of cache by only adding a minimized control circuit in order to be used as main...
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6332182 |
Disk drive control without identification fields
An apparatus and method for disk sector layout, formatting, reading and writing, is based on a flexible formatter microengine that is driven by parameter lists, which may include commands to...
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6324626 |
Semiconductor memory
A semiconductor memory has a main memory and an ID memory, of which both store data in a nonvolatile memory. The data stored in the ID memory is compared with data entered from outside by a...
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6317806 |
Static queue and index queue for storing values identifying static queue locations
A queuing apparatus associated with a processor includes at least one static queue (11), an index generator (34), at least one index queue (37), and a static queue accessing arrangement. Each...
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6314491 |
Peer-to-peer cache moves in a multiprocessor data processing system
A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level 1 cache, and the second processor accesses data using a second level 1 cache. A...
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6314510 |
Microprocessor with reduced context switching overhead and corresponding method
A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working...
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6301647 |
Real mode translation look-aside buffer and method of operation
There is disclosed, for use in an x86-compatible processor capable of operating in real mode and paging mode and having a physically-addressable cache, an address translation device for providing...
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6301646 |
Pointer verification system and method
A system and method for allocating memory blocks and indexing the pointer to the memory blocks in a set of tables. The tables translate the pointers to the memory blocks enabling the efficient...
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6298419 |
Protocol for software distributed shared memory with memory scaling
A method and apparatus for providing additional memory storage within a local node associated with shared memory system is disclosed. A processor associated with a local node of the shared memory...
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6298412 |
Microcomputer and method of determining completion of writing in the microcomputer
When writing of data into nonvolatile memories 8H and 8L is started, data D7 and D15 corresponding to the 128th word of a data input section 8B are inverted and outputted. When accurate writing is...
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6275896 |
Data transfer apparatus and method of the same and data input and output controlling apparatus and method of same
A data transfer apparatus for transferring data between a first storage medium and a second storage medium capable of non-linear access, comprising a temporary storing means for temporarily storing...
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6272604 |
Contingent response apparatus and method for maintaining cache coherency
Each processor (101, 102, 103) in a multiple processor system (100) includes a contingent response unit (121, 122, 123). Each contingent response unit (121, 122, 123) includes a pending operation...
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6266744 |
Store to load forwarding using a dependency link file
A processor employing a dependency link file. Upon detection of a load which hits a store for which store data is not available, the processor allocates an entry within the dependency link file for...
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6266745 |
Method and system in a distributed shared-memory data processing system for determining utilization of nodes by each executed thread
A method and system in a distributed shared-memory data processing system are disclosed for determining a utilization of each of a plurality of coupled processing nodes by one of a plurality of...
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6263410 |
Apparatus and method for asynchronous dual port FIFO
An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f 2 <f 1 <f 2 or 0.5f 1 <f 2 ...
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6260109 |
Method and apparatus for providing logical devices spanning several physical volumes
A method and apparatus for providing very large logical volumes (Meta Device) in a storage system is provided. The storage system includes host controllers and disk controllers which communicate...
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6260115 |
Sequential detection and prestaging methods for a disk storage subsystem
A method for detecting and remembering multiple sequential access patterns made from a host to a memory system having one or more logical storage devices. Once a sequential access pattern is...
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6253297 |
Memory control using memory state information for reducing access latency
A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative...
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6247096 |
Handling eject requests of logical volumes in a data storage subsystem
A method of handling eject requests of logical volumes received by a data storage subsystem from a host system. The method, implemented in computer readable program code, first places identified...
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6240493 |
Method and apparatus for performing access censorship in a data processing system
Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against...
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6237066 |
Supporting multiple outstanding requests to multiple targets in a pipelined memory system
One embodiment of the present invention provides an apparatus that supports multiple outstanding load and/or store requests from an execution engine to multiple sources of data in a computer...
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6233700 |
Method for management of cache page and medium having a cache page management program stored therein
Conventional segment LRU are used to capture data entries. The time that each entry is most recently accessed is stored and held from one entry to another. If a central processing unit encounters a...
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6233646 |
Memory interface controller
The present invention relates to a memory interface controller for a data transmission system. A memory interface controller is capable of randomly accessing a memory using an associative memory...
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6233660 |
System and method for emulating mainframe channel programs by open systems computer systems
A digital computer system comprises a mass storage subsystem and an "open systems" computer system. The mass storage subsystem includes a storage device for storing data and an access control for...
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6233665 |
Mapping shared DRAM address bits by accessing data memory in page mode cache status memory in word mode
A memory system includes a data memory for storing data and applications software and a distinct cache status memory for storing status information regarding the data memory. A memory controller...
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6226716 |
Test driver for use in validating a circuit design
A test driver for use in validating an electronic circuit design is disclosed. The test driver not only provides stimulus and verifies the response of a circuit design, but also responds...
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6212595 |
Computer program product for fencing a member of a group of processes in a distributed processing environment
A computer program product for use in a distributed processing system having a plurality of nodes wherein selected nodes are fenced or unfenced from selected ones of peripheral device server nodes...
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6212608 |
Method and apparatus for thread synchronization in an object-based system
Methods and apparatus which enable threads to lock and to unlock objects disclosed. According to one aspect of the present invention, a method for associating an object with a first thread includes...
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6205510 |
Method for fencing a member of a group of processes in a distributed processing environment
A method for use in a distributed processing system having a plurality of nodes wherein selected nodes are fenced or unfenced from selected ones of peripheral device server nodes in a fence/unfence...
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6199147 |
Distributed-memory multiprocessor computer system with directory-based cache coherency with ambiguous mappings of cached data to main-memory locations
A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient...
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6195732 |
Storage device capacity management
In a data processing system comprising a host system and a memory device including a data storage medium of a predetermined size and corresponding capacity, a secure method of managing available...
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6192484 |
Method and system for recovering lost data
An endeavor is made to enhance system reliability by automatically detecting the status of each HDD at startup, and detecting failures in nonvolatile memory as well so that a failure does not occur...
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6192451 |
Cache coherency protocol for a data processing system including a multi-level memory hierarchy
A data processing system and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of caches and a plurality of processors...
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6189078 |
System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency
A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a...
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6185663 |
Computer method and apparatus for file system block allocation with multiple redo
A shared persistent memory (e.g., disk) file system provides persistent memory block allocation with multiple redo logging of memory blocks. The file system employs a three part block state...
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6178483 |
Method and apparatus for prefetching data read by PCI host
Write posting buffers and read prefetch buffers are arranged in an integrated multiport switch between a PCI interface and an external memory interface. When a PCI host initiates a PCI transaction...
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6175906 |
Mechanism for fast revalidation of virtual tags
A recovery mechanism to eliminate the need to re-fetch cache entries during virtual-to-physical memory re-mapping by reducing accesses and thus the demand on the table lookaside buffer (TLB) during...
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6175900 |
Hierarchical bitmap-based memory manager
A hierarchical bitmap-based memory manager maintains a hierarchical bitmap having an entry for each memory block in a memory heap. Each bitmap entry contains a multi-bit value that represents an...
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6167489 |
System and method for bypassing supervisory memory intervention for data transfers between devices having local memories
A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to...
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6163833 |
Memory managing method for use in a data communications system
A method effectively stores data onto each of buffers included in a storage device of a processor, wherein the data is data being communicated between the processor and each of devices coupled...
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6154796 |
Apparatus and method in a network interface device for storing receiving frame status in a holding register
A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched...
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6145028 |
Enhanced multi-pathing to an array of storage devices
A method, apparatus and article of manufacture for hardware independent system level control of storage units in an array is disclosed. The method comprises the steps of scanning the array of...
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6141734 |
Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol
A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides...
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6141736 |
Arrangement with master and slave units
An arrangement in which at least one master unit is linked via a bus to a multiple of slave units, each slave unit having a memory in which the master unit carries out read and/or write accesses....
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6138188 |
Buffer management device and method for improving buffer usage and access performance in data processing system
A buffer management device and method for improving buffer usage and access performance in a data processing system. A buffer device is located between two components in the data processing system...
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6138211 |
High-performance LRU memory capable of supporting multiple ports
In a high performance microprocessor adopting a superscalar technique, necessarily using a cache memory, TLB, BTB and etc. and being implemented by 4-way set associative, there is provided an LRU...
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