Matches 651 - 700 out of 930 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >
Match Document Document Title
6502171 Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data  
In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same...
6499092 Method and apparatus for performing access censorship in a data processing system  
Method and apparatus for performing access censorship in a data processing system ( 10 ). In one embodiment, a digital data processing system ( 10 ) has a sub-system ( 34 ) that can be protected...
6496907 System and method for updating from a read-only to a read-write entry and concurrently invalidating stale cache copies from head-to-tail and tail-to-head directions  
Cache-coherence computer systems represent cache-lines associated with their processors by linked and shared lists, which can be read-only or read-write. In read-only lists all cache-line copies...
6493806 Method and apparatus for generating a transportable physical level data block trace  
A system and method for generating a transportable physical level data block trace for a computer system. The method comprises capturing a first physical level data block trace on a first computer...
6493807 Updating flash blocks  
The present invention is a system and method for updating memory. The contents of a first storage location in a plurality of storage locations are first copied to a second storage location in the...
6490636 Data processing system for improved input/output command processing  
The present invention has as an object thereof to efficiently execute a plurality of I/O commands in a secondary storage device. The tags of the I/O commands which are issued from a data processing...
6487645 Data storage subsystem with fairness-driven update blocking  
When a primary data storage subsystem receives updates for local storage and mirroring at a counterpart secondary storage subsystem, the primary subsystem institutes device-specific,...
6480942 Synchronized FIFO memory circuit  
A synchronized FIFO memory circuit includes a random access memory and a FIFO controller having a decreased critical-path length. The synchronized FIFO circuit comprises a first counter for...
6480936 Storing apparatus having a dynamic buffer for random or sequential access  
When a write access is received from an upper apparatus, a cache control unit develops write data into a data buffer area in a memory, notifies the upper apparatus of a normal end, and thereafter,...
6473841 Signal processing apparatus with memory access history storage  
In a signal processing apparatus having a memory and plural blocks for accessing the memory provided in an LSI, for the ease of cause analysis in the event of a fault, a trace control block 170 ...
6473839 Device for exchanging data and process for operating it  
A device or arrangement for exchanging data between a main station (master) ( 10 ) and at least one secondary station (slave) ( 12, 12 n ), which each have access to at least one common data line (...
6470432 External storage control device and data transfer method between external storage control devices  
In a data processing system in which main and sub disk storage devices are under the control of individual each disk control devices, the write processing time is reduced by selectively sending...
6467083 Debugging system for computer program, method for checking target program and information storage medium for storing checking program  
A debugging system has a central processing unit, a register group, a tracer and a trace buffer integrated on a single semiconductor chip, a main memory for storing a target program and other data...
6453370 Using of bank tag registers to avoid a background operation collision in memory systems  
A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is...
6453397 Single chip microcomputer internally including a flash memory  
A single chip microcomputer 1 internally includes a flash memory 2 , a communication port 5 , a CPU 4 , an internal ROM 3 , and a programming control circuit 6 . The flash memory 2 ...
6449702 Memory bandwidth utilization through multiple priority request policy for isochronous data streams  
An embodiment of a system logic device for improving memory bandwidth utilization in a computer system with an isochronous data stream includes a FIFO for the isochronous data stream. The FIFO...
6446145 Computer memory compression abort and bypass mechanism when cache write back buffer is full  
In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and...
6442657 Flag generation scheme for FIFOs  
The present invention concerns a circuit comprising a memory, a flag/array address circuit and a flag logic circuit. The memory may be configured to read and write data in response to one or more...
6434678 Method for data storage organization  
A method for fast, high-density data storage in a data storage device having plural storage sections that includes overwriting and reformatting of entire storage sections, each having a large...
6434642 FIFO memory system and method with improved determination of full and empty conditions and amount of data stored  
A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated...
6434675 Method and apparatus for updating data stored in plural storage means in an information processing system  
A storage means control apparatus of this invention includes a first processing unit for performing write processing in a first storage unit, a second processing unit for performing write...
6425048 Memory pool control circuit and memory pool control method  
A memory pool control circuit according to the invention is provided with a CAM (content addressable memory: associative memory) 11 . It further has a monitoring module 12 , an area unlocking...
6421764 Method and apparatus for efficient clearing of memory  
A method and apparatus for clearing memory, or portions thereof in a fast and efficient manner begins by representing a group of memory locations by a representative value. When a particular group...
6421768 Method and system for authentication and single sign on using cryptographically assured cookies in a distributed computer environment  
Cryptographically assured data structures are created to enable a single sign on and/or authentication method for securely transferring user authentication information from a first computer to a...
6415365 Write buffer for use in a data processing apparatus  
The present invention provides a data processing apparatus comprising a processor core for generating addresses identifying locations in a memory and data values for storing in the memory, and a...
6415370 Semiconductor integrated circuit  
Plurality of latch circuits 21, 23 are provided for storing therein written data (D 0 ˜D 7 ), and there is also a register (multiplexed latch circuit) having data bus drivers for storing the...
6408361 Autonomous way specific tag update  
The present invention provides a method and apparatus for allowing autonomous, way specific tag updates. More specifically, the invention provides way specific tag and status updates while...
6408366 Interface device, method and monitoring system for monitoring the status of a hardware device  
A monitoring processing device (SW) comprises a plurality of process means (A, B, C) which monitor a status of a hardware device (HW) by reading status information from an interface device (ID) via...
6405287 Cache line replacement using cache status to bias way selection  
A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice...
6405293 Selectively accessible memory banks for operating in alternately reading or writing modes of operation  
Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while...
6405292 Split pending buffer with concurrent access of requests and responses to fully associative and indexed components  
For a cache-coherent controller for a multiprocessor system sharing a cache memory, a split pending buffer having two components: a fully-associative part and an indexed part that can easily be...
6405295 Data storage apparatus for efficient utilization of limited cycle memory material  
In the semiconductor memory device relating to the present invention, the memory is divided into a plurality of blocks having a plurality of sectors and stores user data in units of sectors. When...
6401163 Apparatus and method for rewriting data from volatile memory to nonvolatile memory  
In an electronic control system having a CPU, a RAM and an EEPROM, an original data stored in the EEPROM is written into the RAM to be updated in a control calculation processing of the CPU. If the...
6401170 RAID systems during non-fault and faulty conditions on a fiber channel arbitrated loop, SCSI bus or switch fabric configuration  
The RAID system disclosed here uses arbitrated fiber channels or switch fabric to connect multiple host computers and storage array controllers (SAC). Each SAC is designated a primary SAC for an...
6393533 Method and device for controlling access to memory  
A computing device ( 12 ) includes a first process ( 16 ) and a second process ( 18 ) executing thereon in conjunction with a local memory ( 20 ). The local memory ( 20 ) stores data files...
6393525 Least recently used replacement method with protection  
An LRU with protection method is provided that offers substantial performance benefits over traditional LRU replacement methods by providing solutions to common problems with traditional LRU...
6393536 Load/store unit employing last-in-buffer indication for rapid load-hit-store  
A load/store unit includes a buffer configured to retain store memory operations which have probed the data cache. Each entry in the buffer includes a last-in-buffer (LIB) indication which...
6385716 Method and apparatus for tracking coherence of dual floating point and MMX register files  
An apparatus and method for tracking coherence between distinct floating point and MMX register files in a microprocessor is provided. The apparatus keeps track of the last time a floating point or...
6378053 Conserving storage space by means of low resolution objects  
The memory space (often in the form of cache) in a system (e.g., an Internet proxy or web browser) is conserved by saving low resolution versions of data objects when the full resolution version is...
6378033 Electronic device, control method thereof and storage medium  
To erase data stored in a flash memory at high speed with simple processing and to improve operation environment, a file stored in the flash memory is managed by small blocks smaller than a...
6374333 Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention  
A novel cache coherency protocol provides a modified-unsolicited (M U ) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system...
6351797 Translation look-aside buffer for storing region configuration bits and method of operation  
There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address...
6349371 Circuit for storing information  
In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect,...
6349369 Protocol for transferring modified-unsolicited state during data intervention  
A novel cache coherency protocol provides a modified-unsolicited (M U ) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system...
6347366 System and method for automatically optimizing software performance  
An embedded genetic allocator system uses genetic algorithms to generate trial solutions to the allocation of data buffers among various kinds of memory banks and measures the quality of each...
6347360 Apparatus and method for preventing cache data eviction during an atomic operation  
Apparatus and method for protecting cache data from eviction during an atomic operation. The apparatus includes a first request queue, a second request queue, and an atomic address block. The first...
6345343 Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state  
A novel cache coherency protocol provides a modified-unsolicited (M U ) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system...
6345344 Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits  
A novel cache coherency protocol provides a modified-unsolicited (M u ) cache state to indicate that a value held in 5 a cache line has been modified (i.e., is not currently consistent with system...
6345348 Memory system capable of supporting different memory devices and a memory device used therefor  
A memory includes an ROM portion storing information specific to the memory, and transfers the stored information to a memory controller via an output buffer and a sink link. The memory controller...
6345342 Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line  
A novel cache coherency protocol provides a modified-unsolicited (M u ) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system...
Matches 651 - 700 out of 930 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >