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7636817 |
Methods and apparatus for allowing simultaneous memory accesses in a programmable chip system
Methods and apparatus are provided for allowing simultaneous memory accesses. A generator tool analyzes logic to determine the number of simultaneous memory accesses to the same data structure....
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7634622 |
Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory
A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different...
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7634621 |
Register file allocation
Circuits, methods, and apparatus that provide the die area and power savings of a single-ported memory with the performance advantages of a multiported memory. One example provides register...
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7620780 |
Multiprocessor system with cache controlled scatter-gather operations
Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the...
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7620784 |
High speed nonvolatile memory device using parallel writing among a plurality of interfaces
Described is a high speed nonvolatile memory device and technology that includes a controller coupled via interfaces to sets of nonvolatile storage, such as separate flash memory chips or separate...
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7617367 |
Memory system including a two-on-one link memory subsystem interconnection
A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a...
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7613065 |
Multi-port memory device
In a multi-port memory device, a plurality of ports simultaneously access a plurality of banks through global data buses. A data conflict detector compares valid data signals input from the...
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7613886 |
Methods and apparatus for synchronizing data access to a local memory in a multi-processor system
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
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7610451 |
Data transfer mechanism using unidirectional pull bus and push bus
A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory...
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7606982 |
Multi-path accessible semiconductor memory device having data transmission mode between ports
A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to...
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7600081 |
Processor architecture having multi-ported memory
A processing system comprises a multiport memory module having N ports, N data communication buses, and N hardware acceleration modules that communicate with a respective one of the N ports on a...
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7596666 |
Multi-path accessible semiconductor memory device having port state signaling function
A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path...
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7590719 |
System and a method for blocking off processors when communication paths between adapters and a cache memory are determined to be secure
The invention relates to exchanging micro programs in a storage device, automatically, without halting operation. In one embodiment, the path adapters of a host computer are connected to the...
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7584228 |
System and method for duplication of virtual private server files
A method and system for managing files in a server environment includes launching a plurality of Virtual Private Servers (VPSs) in a computing system; copying a content of a file of a VPS to a...
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7577059 |
Decoding control with address transition detection in page erase function
Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A...
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7577774 |
Independent source read and destination write enhanced DMA
The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to...
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7577799 |
Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture
The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at...
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7571287 |
Multiport memory architecture, devices and systems including the same, and methods of using the same
A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive...
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7568074 |
Time based data storage for shared network memory switch
A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming...
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7565496 |
Sharing memory among multiple information channels
Memory is shared among multiple information channels, which may be of particular use for storing streams of packets. Memory allocation information is maintained which can be used to identify the...
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7565563 |
Non-volatile memory arrangement and method in a multiprocessor device
This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into...
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7562193 |
Memory with single and dual mode access
The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within...
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7549001 |
Digital RAM memory circuit with an expanded command structure
Methods, systems, and articles of manufacture for transferring control commands to a memory device. In one embodiment, the memory device comprises at least one serial command terminal with a...
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7546424 |
Embedded processor with dual-port SRAM for programmable logic
Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a...
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7539825 |
Multi-port memory device providing protection signal
A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes:...
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7536516 |
Shared memory device
A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of...
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7536499 |
Memory access control device and processing system having same
A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a...
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7533222 |
Dual-port SRAM memory using single-port memory cell
A dual-port memory system is implemented using single-port memory cells. An access arbiter having a synchronization circuit is used to prioritize and synchronize the access requests associated with...
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7529894 |
Use of FBDIMM channel as memory channel and coherence channel
In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit...
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7529139 |
N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof
Method and memory circuits capable of allowing M memory addresses of an N-port memory to be accessed concurrently, wherein N and M both are a natural number, and M is larger than N. Accordingly, a...
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7523270 |
Multi-port memory device
A multi-port memory device has a plurality of ports which are connected to different external devices with the memory device performing serial data communication independently. The memory device...
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7519779 |
Dumping using limited system address space
Method and apparatus for reading the internal address space of an adapter in a system during a dump are described. The adapter includes a control port and a data port used as channels for...
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7516265 |
System and method for providing an application with memory access methods
A system for providing an application with a plurality of methods for accessing memory of a programmable logic controller includes an application, an interface for establishing communication...
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7516280 |
Pulsed arbitration system and method
A pulsed arbitration system has a partial-address coincidence detector with a partial-address collision flag as an output. An active global word line detector and disable pulse generator receives...
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7512837 |
System and method for the recovery of lost cache capacity due to defective cores in a multi-core chip
A method for recovering lost cache capacity in a multi core chip having at least one defective core including identifying the cores contained in the chip that are viable cores and identifying at...
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7495793 |
Image processing method, image processing apparatus, and print apparatus that uses image data recorded on an image record medium
When a memory card is placed in a printer, a service layer requests a file list manager to create an image information list. When the memory card is removed, the service layer requests the file...
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7493427 |
Apparatus and method for supporting received data processing in an offload of network protocol processing
A number of improvements in network adapters that offload protocol processing from the host processor are provided. Specifically, an improved mechanism for handling receipt of data packets in a...
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7489318 |
Apparatus and method for managing memory to generate a texture from a render target when forming graphical images
An exemplary method detects an update to data representing a portion of a render target, according to one embodiment of the invention. Also, this method forms a copy of the portion configured to be...
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7490208 |
Architecture for compact multi-ported register file
Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port...
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7472235 |
Multi-interfaced memory
A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface share an address bus and a data bus....
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7472236 |
Managing mirrored memory transactions and error recovery
In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In...
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7464228 |
System and method to conserve conventional memory required to implement serial ATA advanced host controller interface
An information handling system includes a processor and a system memory coupled to the processor. The system has a plurality of persistent mass storage devices including first and second storage...
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7421559 |
Apparatus and method for a synchronous multi-port memory
A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access...
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7406564 |
Distributed FIFO
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or...
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7405980 |
Shared terminal memory interface
A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an...
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7404058 |
Method and apparatus for avoiding collisions during packet enqueue and dequeue
A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication...
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7404044 |
System and method for data transfer between multiple processors
A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In...
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7394884 |
Synchronizing method
To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the...
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7383399 |
Method and apparatus for memory compression
Memory apparatus and methods for memory compression. A memory agent may comprise a compression engine to compress or decompress data in the agent without sending the data on the host memory...
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7376175 |
Wireless communications systems and methods for cache enabled multiple processor based multiple user detection
The invention provides methods and apparatus for multiple user detection (MUD) processing. One aspect of the invention provides a multiprocessor, multiuser detection system for detecting user...
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