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9037809 Memory module with circuit providing load isolation and noise reduction  
Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a...
9037761 Configurable buffer allocation for multi-format video processing  
Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The...
9032162 Systems and methods for providing memory controllers with memory access request merging capabilities  
An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests...
9032161 Storage system control method  
An apparatus for copying data to another apparatus including a receiving buffer, includes: a transmitting buffer including a plurality of areas for temporary storing data of the copying; and a...
9026746 Signal control device and signal control method  
A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports,...
9003121 Multi-ported memory with multiple access support  
A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of...
8996795 Storage device for mounting to a host  
A storage device comprising a non-volatile memory for storing data, and an input device that is operative to select an operating mode of the storage device prior to mounting the storage device,...
8996822 Multi-device memory serial architecture  
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second...
8990515 Aliasing buffers  
The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of...
8990516 Multi-core shared memory system with memory port to memory space mapping  
A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a...
8972689 Apparatus, method and system for using real-time performance feedback for modeling and improving access to solid state media  
A storage processor identifies latency of memory drives for different numbers of concurrent storage operations. The identified latency is used to identify debt limits for the number of concurrent...
8959291 Two-port memory capable of simultaneous read and write  
Described embodiments provide a multi-port memory system that has a plurality of memory banks and an equal number of mapping memory banks, each one of the data memory banks corresponding to one of...
8937965 Storage system comprising function for migrating virtual communication port added to physical communication port  
A switch unit, which is connected to one or more computers and one or more storage systems, comprises an update function for updating transfer management information (a routing table, for...
8935486 Memory access for digital signal processing  
Memory access in a digital signal processing system is described. In one example, the digital signal processing system comprises a multi-port memory that is constructed from a memory interface...
8930595 Memory switch for interconnecting server nodes  
Described is a data switching device comprising a plurality of input ports, a plurality of output ports, a plurality of first conductive connectors, a plurality of second conductive connectors, a...
8930643 Multi-port memory and operation  
Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or...
8930641 Systems and methods for providing memory controllers with scheduler bypassing capabilities  
An integrated circuit may have a memory controller that interfaces between master processing modules and system memory. A scheduling module may be used to handle memory access requests received...
8930642 Configurable multi-port memory device and method thereof  
Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The...
8918615 Information storage system including a plurality of storage systems that is managed using system and volume identification information and storage system management method for same  
An embodiment of this invention is an information storage system comprising a plurality of storage systems connected to be able to communicate. Each of the plurality of storage systems includes...
8918594 Multi-interface memory with access control  
Apparatus and methods disclose techniques to control access to a memory array. The memory array can be accessed by either a first interface or a second interface. A switch register grants...
8914649 Bios controlled peripheral device port power  
A computing device (101, 400, 500) has a processor (401) and at least one peripheral device port (106, 107, 108, 109, 410-1 to 410-5). The processor (401) is configured to selectively power the at...
8892825 Method and system for improving serial port memory communication latency and reliability  
A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the...
8878860 Accessing memory using multi-tiling  
An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals....
8880812 WWN table management systems and methods  
A serial attached small computer systems interface (SAS) module includes a first port with (i) a first physical layer device and (ii) a first port control module. The first physical layer device...
8862831 Method and apparatus to facilitate shared pointers in a heterogeneous platform  
A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to,...
8856491 Garbage collection implemented in hardware  
A computing device is provided and includes a memory module, a sweep engine, a root snapshot module, and a trace engine. The memory module has a memory implemented as at least one hardware...
8856262 Cloud-based image hosting  
Data including information regarding a display of the host device may be received. A display of a client device may correspond to the display of the host device. Information regarding the display...
8850128 Implementing data storage and dual port, dual-element storage device  
A method for implementing data storage and a dual port, dual element storage device are provided. A storage device includes a predefined form factor including a first port and a second port, and a...
8832388 Managing shared memory used by compute nodes  
A technology can be provided for managing shared memory used by a plurality of compute nodes. An example system can include a shared globally addressable memory to enable access to shared data by...
8825632 Method of interrogating a database and interrogation device  
A method of interrogation or modification of a database having a plurality of tables each with fields and relationships between the fields of various tables, the method including: filling in a...
8825966 Reduced pin count interface  
An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count...
8806150 Computer system and Fibre Channel migration method  
A computer system in which one or more host computers 30 having a FC (Fiber Channel) node port and one or more storage apparatuses 40 having a FC node port are coupled via a FC fabric. The storage...
8782646 Non-uniform memory access (NUMA) enhancements for shared logical partitions  
In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in...
8782350 Circuit providing load isolation and noise reduction  
Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a...
8775744 Simultaneous switching of multiple time slots in an optical network node  
A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one...
8769214 External memory controller node  
A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a...
8769213 Multi-port memory and operation  
Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or...
8762653 Dynamic QoS upgrading  
In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for...
8762620 Multiprocessor storage controller  
A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In...
8745335 Memory arbiter with latency guarantees for multiple ports  
Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between...
8732384 Method and apparatus for memory access  
A device and methods are provided for accessing memory. In one embodiment, a method includes receiving a request for data stored in a device, checking a local memory for data based on the request...
8732400 Data store maintenance requests in interconnects  
Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one...
8726064 Interconnection system  
An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths...
8711652 Arbitration for memory device with commands  
A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The...
8700866 Data transfer apparatus, data transfer device, and data transfer method in a data transfer device  
A data transfer apparatus includes: a first port and a second port that communicate data; a memory unit that stores the data; and a securing unit that secures, when a first time period starting...
8700857 Optimizing memory copy routine selection for message passing in a multicore architecture  
In one embodiment, the present invention includes a method to obtain topology information regarding a system including at least one multicore processor, provide the topology information to a...
8688877 Multiport memory architecture  
The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data....
8677070 Cache memory control apparatus and cache memory control method  
According to an aspect of the embodiment, an FP includes a plurality of entries which holds requests to be processed, and each of the plurality of entries includes a requested flag indicating that...
8677068 Scalable storage devices  
Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A...
8671238 Robust live migration using shared filesystem  
A method for transferring guest physical memory from a source host to a destination host during live migration of a virtual machine (VM) involves creating a file on a shared datastore, the file on...