|
Match
|
Document |
Document Title |
|
|
7620787 |
Optimizing memory accesses for network applications using indexed register files
A processing device includes an optimizer to migrate objects from an external memory of a network processing to local memory device to registers connected to a processor. The optimizer further...
|
|
|
7620696 |
System and method for conflict responses in a cache coherency protocol
A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response...
|
|
|
7617371 |
Storage controller and method for controlling the same
An object of the present invention is to provide a storage controller capable of facilitating extension of storage capacity while suppressing investment related to storage capacity. The present...
|
|
|
7616651 |
System and method for communicating data packets
A method for communicating data packets is provided that includes receiving a data packet at a first processor. A packet handle and interface handle are attached to the data packet. The packet...
|
|
|
7614078 |
Threshold access based upon stored credentials
A method and apparatus for authorizing an access requester to access a data communication network is provided. A determination is made that a threshold access control server cannot process an...
|
|
|
7613961 |
CPU register diagnostic testing
One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of...
|
|
|
7613886 |
Methods and apparatus for synchronizing data access to a local memory in a multi-processor system
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
|
|
|
7613885 |
Cache coherency control method, chipset, and multi-processor system
In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for...
|
|
|
7613884 |
Multiprocessor system and method ensuring coherency between a main memory and a cache memory
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a...
|
|
|
7613065 |
Multi-port memory device
In a multi-port memory device, a plurality of ports simultaneously access a plurality of banks through global data buses. A data conflict detector compares valid data signals input from the...
|
|
|
7610611 |
Prioritized address decoder
A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address...
|
|
|
7610200 |
System and method for controlling sound data
A system and method for controlling access to parameter blocks of a sound processor. According to the method and system disclosed herein, the present invention includes a host, a sound processor...
|
|
|
7606982 |
Multi-path accessible semiconductor memory device having data transmission mode between ports
A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to...
|
|
|
7606978 |
Multi-node computer system implementing global access state dependent transactions
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to...
|
|
|
7602512 |
Method and apparatus for authentication in secure printing
Secrecy of printed matter is raised and charges for a storing area are more accurately charged. According to the invention, a printing apparatus is instructed so as to store print data...
|
|
|
7600080 |
Avoiding deadlocks in a multiprocessor system
In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a...
|
|
|
7600065 |
Arbitration scheme for shared memory device
For arbitrating access to a shared memory device among a plurality of masters, a master generates a request for access signal that is sent to the arbitrator concurrently with an indispensable...
|
|
|
7599999 |
System and methodology that facilitates client and server data exchange in a distributed industrial automation environment
The present invention relates to a system and methodology providing a multi-protocol data exchange between client and server components in an industrial automation environment. According to one...
|
|
|
7590805 |
Monitor implementation in a multicore processor with inclusive LLC
A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always...
|
|
|
7587577 |
Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content
A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing...
|
|
|
7587557 |
Data sharing apparatus and processor for sharing data between processors of different endianness
The data sharing apparatus in the present invention includes a first processor and a second processor, each of a different endianness, that are both connected to the memory via the data bus, in a...
|
|
|
7587310 |
Sound processor architecture using single port memory unit
A system and method for implementing a sound processor. The sound processor includes a first voice engine, a second voice engine, and at least one single-port memory unit. An operation of the first...
|
|
|
7584332 |
Computer systems with lightweight multi-threaded architectures
Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.
|
|
|
7584228 |
System and method for duplication of virtual private server files
A method and system for managing files in a server environment includes launching a plurality of Virtual Private Servers (VPSs) in a computing system; copying a content of a file of a VPS to a...
|
|
|
7581172 |
Method and apparatus for efficient management of XML documents
A storage manager represents XML-compliant documents as a collection of objects, each associated with an element of the XML document. The objects are created with a hierarchy that conforms to the...
|
|
|
7581069 |
Multiple computer system with enhanced memory clean up
The updating of only some memory locations in a multiple computer environment in which at least one applications program ( 50 ) executes simultaneously on a plurality of computers M 1 , M 2 . . ....
|
|
|
7581061 |
Data migration using temporary volume to migrate high priority data to high performance storage and lower priority data to lower performance storage
The storage control device of the present invention uses a temporary volume to move data rapidly between volume groups. The storage control device forms a plurality of volume groups by grouping...
|
|
|
7581060 |
Storage device control apparatus and control method for the storage device control apparatus
A storage device control apparatus includes a mounting part and an internal connection part. The mounting part can removably mount channel control unit, each with a host interface controller formed...
|
|
|
7581056 |
Load balancing using distributed front end and back end virtualization engines
Methods and apparatus are provided for improving network virtualization in a storage area network. A virtualization engine is divided into a front end virtualization engine and a back end...
|
|
|
7577813 |
System and method for enumerating multi-level processor-memory affinities for non-uniform memory access systems
A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a...
|
|
|
7577802 |
Accessing a reservable device by transiently clearing a persistent reservation on the device in multi-host system
Systems, methods, and computer program products are presented for transiently clearing a reservation on a device, where the reservation belongs to a host that owns the device and the reservation...
|
|
|
7577799 |
Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture
The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at...
|
|
|
7577798 |
Space-adaptive lock-free queue using pointer-sized single-target synchronization
Many conventional lock-free data structures exploit techniques that are possible only because state-of-the-art 64-bit processors are still running 32-bit operating systems and applications. As...
|
|
|
7571289 |
Disk array device and reservation cancellation control method for disk array device
The present invention allows a reserved state that prevails for an LDEV as a result of a host undergoing a system shutdown or the like to be confirmed and cancelled easily. The server 1 reserves...
|
|
|
7571288 |
Scalable rundown protection for object lifetime management
Object rundown protection that scales with the number of processors in a shared-memory computer system is disclosed. Prior to object rundown, a cache-aware reference count data structure is used to...
|
|
|
7568077 |
Information processing apparatus and file controller
An information processing apparatus, including: a file memory to store data; a file controller to access the file memory; a first control section to manage the file memory via the file controller;...
|
|
|
7568074 |
Time based data storage for shared network memory switch
A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming...
|
|
|
7568066 |
Reset system for buffer and method thereof
A reset system for a buffer and a method thereof are disclosed. The reset system of the present invention includes a resettable flag in the buffer and a control unit. The reset method is to set the...
|
|
|
7568013 |
Multiple message send routine for network packets
A method for sending a plurality of messages to a plurality of recipients including obtaining the plurality of messages for the plurality of recipients, grouping the plurality of messages into a...
|
|
|
7567992 |
Replicating of plurality of instances of an object model in memory arrangement using portable object references where each object attribute assigned GUID
Various approaches for managing a plurality of instances of an object model are disclosed. At least a first and a second instance of the object model are established in first and second data...
|
|
|
7562193 |
Memory with single and dual mode access
The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within...
|
|
|
7562109 |
Connectivity confirmation method for network storage device and host computer
The present invention decreases the burden of operation required for specifying the continuity status and the cause of failure of a network storage device. A host computer accepts the specification...
|
|
|
7558920 |
Apparatus and method for partitioning a shared cache of a chip multi-processor
A method and apparatus for partitioning a shared cache of a chip multi-processor are described. In one embodiment, the method includes a request of a cache block from system memory if a cache miss...
|
|
|
7558912 |
Disk array system
A technique to distribute processing to meet a request from other system without partializing the processing to specific processor and can execute processing efficiently while adopting...
|
|
|
7555653 |
Data processing apparatus, program for use therewith, and method for use therewith
A data processing apparatus is provided which is capable of improving the responsiveness of communication in which only a maximum of one access request source has write authorization and the other...
|
|
|
7555597 |
Direct cache access in multiple core processors
Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and...
|
|
|
7555527 |
Efficiently linking storage object replicas in a computer network
A system and method for efficiently linking together replicas of a storage object. The location of a first replica of the storage object may be stored on a node in a network. When new replicas of...
|
|
|
7552295 |
Maintaining consistency when mirroring data using different copy technologies
Provided are a method, system, and program for maintaining consistency when mirroring data using different copy technologies. Update groups having updates to primary storage locations are formed...
|
|
|
7549024 |
Multi-processing system with coherent and non-coherent modes
An integrated circuit comprising a plurality of processor cores operable to perform respective data processing operations, at least one of said processor cores being configurable to operate either...
|
|
|
7548918 |
Techniques for maintaining consistency for different requestors of files in a database management system
A method and apparatus for providing file system operation locks at a database server is provided. A database server may employ database locks and file system operation locks in servicing requests...
|